Patrick J. Quinn

17 papers C 2Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2020 — conf
A 0.037mm
ECCTD
Georgi I. Radulov, Patrick J. Quinn
2015 J jnl
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund
2015 J jnl
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.
IEEE Trans. Very Large Scale Integr. Syst.
Georgi I. Radulov, Patrick J. Quinn, Arthur H. M. van Roermund
2008 — conf
A flexible 12-bit self-calibrated quad-core current-steering DAC.
APCCAS
Georgi I. Radulov, Patrick J. Quinn, Hans Hegt, Arthur H. M. van Roermund
2007 C conf
Parallel current-steering D/A Converters for Flexibility and Smartness.
ISCAS
Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund
2006 C conf
A binary-to-thermometer decoder with built-in redundancy for improved DAC yield.
ISCAS
Georgi I. Radulov, Patrick J. Quinn, Pieter C. W. van Beek, Johannes A. Hegt, Arthur H. M. van Roermund
2005 — conf
A start-up calibration method for generic current-steering D/A converters with optimal area solution.
ISCAS (1)
Georgi I. Radulov, Patrick J. Quinn, Johannes A. Hegt, Arthur H. M. van Roermund
2005 — conf
Accuracy limitations of pipelined ADCs.
ISCAS (3)
Patrick J. Quinn, Arthur H. M. van Roermund
2005 — conf
An on-chip self-calibration method for current mismatch in D/A converters.
ESSCIRC
Georgi I. Radulov, Patrick J. Quinn, Hans Hegt, Arthur H. M. van Roermund
2005 — conf
Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs.
ISCAS (3)
Patrick J. Quinn, Arthur H. M. van Roermund
2005 — conf
Smart AD and DA converters.
ISCAS (4)
Arthur H. M. van Roermund, Hans Hegt, Pieter Harpe, Georgi I. Radulov, Athon Zanikopoulos, Konstantinos Doris, Patrick J. Quinn
2004 — conf
Producing a DVD for Use in Diabetes Education.
CATE
Patrick J. Quinn, John Lynn
2003 — conf
A CMOS single-ended OTA with high CMRR.
ESSCIRC
Maxim Pribytko, Patrick J. Quinn
2003 — conf
Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS.
CICC
Patrick J. Quinn, Maxim Pribytko
2003 J jnl
Capacitor matching insensitive algorithmic ADC requiring no calibrations.
Integr.
Patrick J. Quinn, Maxim Pribytko
2000 J jnl
A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation.
IEEE J. Solid State Circuits
Patrick J. Quinn, Koen van Hartingsveldt, Arthur H. M. van Roermund
1998 J jnl
High-accuracy charge-redistribution SC video bandpass filter in standard CMOS.
IEEE J. Solid State Circuits
Patrick J. Quinn