Patrick Girard

332 papers A* 4A 42B 29C 43Misc 21Journal 90Unranked 102

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	FN2LD: FeFET-based nonvolatile and node-upset-recovery latch designs with cost optimization. Microelectron. J. Aibin Yan, Wangjin Jiang, Haotian Wang, Biying Kang, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard
2026	J	`jnl`	NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing. IEEE Trans. Very Large Scale Integr. Syst. Aibin Yan, Yue Zhang, Litao Wang, Zhengfeng Huang, Qingyang Zhang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2025	C	`conf`	A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation. IOLTS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, T. Vayssade, Arnaud Virazel
2025	C	`conf`	A Runtime Efficient Graph-Based Cell-Aware Model Generation for Structural SRAM Testing. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	A	`conf`	Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory. DATE Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2025	J	`jnl`	Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aibin Yan, Yuting He, Zhengfeng Huang, Wenjie Yan, Jie Cui, Xiaolei Wang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement. IEEE Trans. Very Large Scale Integr. Syst. Aibin Yan, Changli Hu, Jing Li, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Chao Zhou, Tianming Ni, Jing Zhang, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS. IEEE Trans. Very Large Scale Integr. Syst. Aibin Yan, Yongkang Xu, Yue Zhang, Na Bai, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	Graph-Based Multitask Transfer Learning for Fault Detection and Diagnosis of Few-Shot Analog Circuits. IEEE Internet Things J. Zhongyu Gao, Aibin Yan, Zhengfeng Huang, Jie Cui, Byeong-Hee Roh, Guangzhu Liu, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xing Guo, Jiajia Zhang, Xu Meng, Zhenmin Li, Xiaoqing Wen, Patrick Girard, Bin Liang, Aibin Yan
2025	—	`conf`	Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment. DFT D. Ronga, Eric Faehn, Patrick Girard, Arnaud Virazel
2025	A	`conf`	NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead. DATE Aibin Yan, Wangjin Jiang, Han Bao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard
2025	J	`jnl`	Nonvolatile Double- and Triple-Node-Upset Tolerant Latch Designs Based on FeFET and CMOS. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Biying Kang, Wangjin Jiang, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	QtNURAV: A Robust Latch Design With Quintuple Node Upset Recovery and Algorithm Based Verifications for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Jing Li, Han Bao, Tianming Ni, Zhengfeng Huang, Bin Liang, Patrick Girard, Xiaoqing Wen
2025	J	`jnl`	SRAM Periphery Testing Using the Cell-Aware Test Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2025	C	`conf`	TNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications. ISCAS Aibin Yan, Zhiyuan Pei, Xing Guo, Jie Song, Cuiyun Jiang, Huaguo Liang, Xiaoqing Wen, Patrick Girard
2025	J	`jnl`	TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications. IEEE Trans. Very Large Scale Integr. Syst. Aibin Yan, Jiajia Zhang, Xiumin Xu, Hanxiang Li, Na Bai, Zhengfeng Huang, Xiaolei Wang, Xiaoqing Wen, Patrick Girard
2025	J	`jnl`	Triple-Node-Upset Recovery High-Impedance-State-Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Zhuoyuan Lin, Yongkang Xu, Na Bai, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2024	A	`conf`	A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. ITC Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	C	`conf`	A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS Gianmarco Mongelli, Xhesila Xhafa, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel
2024	A	`conf`	A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2024	—	`conf`	A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology. DFT Xhesila Xhafa, Eric Faehn, Patrick Girard, Arnaud Virazel
2024	J	`jnl`	FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell. IEEE Trans. Circuits Syst. II Express Briefs Aibin Yan, Yu Chen, Zhongyu Gao, Tianming Ni, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
2024	—	`conf`	IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI Aibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen
2024	J	`jnl`	MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aibin Yan, Zhixing Li, Zhongyu Gao, Jing Zhang, Zhengfeng Huang, Tianming Ni, Jie Cui, Xiaolei Wang, Patrick Girard, Xiaoqing Wen
2024	J	`jnl`	Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. IEEE Trans. Very Large Scale Integr. Syst. Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2024	C	`conf`	Nonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices. ISCAS Aibin Yan, Zhuoyuan Lin, Guangzhu Liu, Qingyang Zhang, Zhengfeng Huang, Jie Cui, Xiaoqing Wen, Patrick Girard
2024	—	`conf`	Producing a Bidirectional ATPG Compliant Verilog-HDL Memory Model of SRAM. DTTIS D. Ronga, Xhesila Xhafa, Eric Faehn, Patrick Girard, Thibault Vayssade, Arnaud Virazel
2023	J	`jnl`	A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications. IEEE Des. Test Aibin Yan, Yuting He, Xiaoxiao Niu, Jie Cui, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2023	—	`conf`	A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications. ACM Great Lakes Symposium on VLSI Aibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui, Jie Song, Tianming Ni, Patrick Girard, Xiaoqing Wen
2023	—	`conf`	A Low Overhead and Double-Node-Upset Self-Recoverable Latch. ITC-Asia Aibin Yan, Fan Xia, Tianming Ni, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2023	—	`conf`	Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications. ITC-Asia Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
2023	C	`conf`	Design of Low-Cost Approximate CMOS Full Adders. ISCAS Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2023	—	`conf`	Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness. ITC-Asia Aibin Yan, Chao Zhou, Shaojie Wei, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2023	J	`jnl`	Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Aibin Yan, Runqi Liu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang
2023	J	`jnl`	Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2023	A	`conf`	High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. DATE Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2023	B	`conf`	Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2023	J	`jnl`	LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aibin Yan, Zhixing Li, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2023	B	`conf`	Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS Xhesila Xhafa, Patrick Girard, Arnaud Virazel
2023	B	`conf`	On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory di Pendina, Patrick Girard, Arnaud Virazel
2023	A	`conf`	Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. ITC Julia Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
2023	J	`jnl`	Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications. IEEE Trans. Emerg. Top. Comput. Aibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang
2023	J	`jnl`	Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications. Microelectron. J. Aibin Yan, Jing Xiang, Yang Chang, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
2022	A	`conf`	A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. ITC P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
2022	B	`conf`	A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS Julia Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel
2022	Misc	`conf`	A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications. VTS Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2022	—	`conf`	A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology. ACM Great Lakes Symposium on VLSI Aibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui, Yong Zhou, Tianming Ni, Patrick Girard, Xiaoqing Wen
2022	—	`conf`	A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage. ATS Aibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui, Patrick Girard, Xiaoqing Wen
2022	J	`jnl`	All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. ACM J. Emerg. Technol. Comput. Syst. Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
2022	J	`jnl`	Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard, Xiaoqing Wen
2022	—	`conf`	Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. ITC-Asia Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard
2022	B	`conf`	Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2022	J	`jnl`	Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments. IEEE Trans. Emerg. Top. Comput. Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2022	A	`conf`	SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments. DATE Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard
2022	—	`conf`	Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications. ACM Great Lakes Symposium on VLSI Aibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2022	—	`ch.`	Test and Reliability of Approximate Hardware. Approximate Computing Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel
2022	—	`conf`	Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. ACM Great Lakes Symposium on VLSI Aibin Yan, Zhihui He, Jing Xiang, Jie Cui, Yong Zhou, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2021	—	`conf`	A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments. ACM Great Lakes Symposium on VLSI Aibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard, Xiaoqing Wen
2021	A	`conf`	A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC Julia Lefevre, Philippe Debaud, Patrick Girard, Arnaud Virazel
2021	A	`conf`	A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
2021	J	`jnl`	A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
2021	—	`conf`	Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2021	J	`jnl`	DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Trans. Very Large Scale Integr. Syst. Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
2021	B	`conf`	Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata. ETS Syed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard, Michael Waltl
2021	J	`jnl`	Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications. J. Electron. Test. Aibin Yan, Aoran Cao, Zhelong Xu, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen
2021	J	`jnl`	Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications. Microelectron. J. Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2021	B	`conf`	Emerging Computing Devices: Challenges and Opportunities for Test and Reliability ETS Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
2021	J	`jnl`	Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
2021	—	`conf`	Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
2021	C	`conf`	Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
2021	C	`conf`	Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel
2021	—	`conf`	Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard
2020	C	`conf`	A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza
2020	A	`conf`	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	J	`jnl`	A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Zhelong Xu, Kang Yang, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2020	—	`conf`	A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets. ATS Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard
2020	J	`jnl`	A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	C	`conf`	An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM. IOLTS Panagiota Papavramidou, Michael Nicolaidis, Patrick Girard
2020	—	`conf`	DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ISQED Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
2020	J	`jnl`	Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications. IEEE Trans. Aerosp. Electron. Syst. Aibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2020	—	`conf`	Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. ITC-Asia Zhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
2020	B	`conf`	Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
2020	C	`conf`	Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
2020	C	`conf`	Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications. ISCAS Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen
2020	A*	`conf`	HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. DAC Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen
2020	C	`conf`	Impact of Aging on Soft Error Susceptibility in CMOS Circuits. IOLTS Ambika Prasad Shah, Patrick Girard
2020	J	`jnl`	Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment. IEEE Trans. Computers Aibin Yan, Yuanjie Hu, Jie Cui, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen
2020	B	`conf`	Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	A	`conf`	Maximizing Yield for Approximate Integrated Circuits. DATE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	J	`jnl`	Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets. IEEE Trans. Circuits Syst. Aibin Yan, Yan Chen, Yuanjie Hu, Jun Zhou, Tianming Ni, Jie Cui, Patrick Girard, Xiaoqing Wen
2020	J	`jnl`	On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. Bastien Deveautour, Arnaud Virazel, Patrick Girard, Valentin Gherman
2020	B	`conf`	QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard
2020	J	`jnl`	Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs. IEEE Trans. Circuits Syst. I Regul. Pap. Aibin Yan, Yafei Ling, Jie Cui, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard, Xiaoqing Wen
2019	—	`conf`	A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS Hassen Aziza, Mathieu Moreau, Annie Pérez, Arnaud Virazel, Patrick Girard
2019	—	`conf`	Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications. ATS Aibin Yan, Zhen Wu, Jun Zhou, Yuanjie Hu, Yan Chen, Zuobin Ying, Xiaoqing Wen, Patrick Girard
2019	J	`jnl`	Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets. IEEE Access Aibin Yan, Jun Zhou, Yuanjie Hu, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2019	—	`conf`	Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications. ATS Aibin Yan, Zhen Wu, Lu Lu, Zhili Chen, Jie Song, Zuobin Ying, Patrick Girard, Xiaoqing Wen
2019	C	`conf`	Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
2018	J	`jnl`	A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics. J. Low Power Electron. Patrick Girard
2018	A	`conf`	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
2018	—	`conf`	Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	—	`conf`	Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS Bastien Deveautour, Arnaud Virazel, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman
2018	C	`conf`	On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	—	`conf`	Power-aware testing in the Era of IoT. ISQED Patrick Girard
2018	J	`jnl`	Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
2018	—	`conf`	Testing approximate digital circuits: Challenges and opportunities. LATS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	J	`jnl`	A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	J	`jnl`	A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2017	—	`conf`	An effective fault-injection framework for memory reliability enhancement perspectives. DTIS G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
2017	—	`conf`	Approximate computing: Design & test for integrated circuits. LATS Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi
2017	J	`jnl`	HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	J	`jnl`	Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2017	C	`conf`	Towards approximation during test of Integrated Circuits. DDECS Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	—	`conf`	Towards digital circuit approximation by exploiting fault simulation. EWDTS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2016	J	`jnl`	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
2016	C	`conf`	A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	C	`conf`	A hybrid power modeling approach to enhance high-level power models. DDECS Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	B	`conf`	A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2016	J	`jnl`	An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel, Patrick Girard
2016	—	`conf`	An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
2016	C	`conf`	An effective approach for functional test programs compaction. DDECS Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Auto-adaptive ultra-low power IC. DTIS Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
2016	J	`jnl`	Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
2016	—	`conf`	Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Test of low power circuits: Issues and industrial practices. ICECS Alberto Bosio, Patrick Girard, Arnaud Virazel
2015	—	`conf`	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
2015	—	`conf`	An effective ATPG flow for Gate Delay Faults. DTIS Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	B	`conf`	An effective hybrid fault-tolerant architecture for pipelined cores. ETS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
2015	—	`conf`	An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2015	C	`conf`	Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2015	C	`conf`	Design-for-Diagnosis Architecture for Power Switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
2015	A	`conf`	Exploring the impact of functional test programs re-used for power-aware testing. DATE Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	Scan-chain intra-cell defects grading. DTIS Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2014	J	`jnl`	A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
2014	—	`conf`	A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
2014	—	`conf`	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	J	`jnl`	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2014	C	`conf`	An intra-cell defect grading tool. DDECS Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
2014	J	`jnl`	Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2014	J	`jnl`	Intra-Cell Defects Diagnosis. J. Electron. Test. Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
2014	J	`jnl`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. IEICE Trans. Inf. Syst. Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2014	—	`conf`	On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
2014	J	`jnl`	On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
2014	C	`conf`	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	—	`conf`	Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
2014	Misc	`conf`	TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Test and diagnosis of power switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2014	C	`conf`	Timing-aware ATPG for critical paths with multiple TSVs. DDECS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	B	`conf`	iBoX - Jitter based Power Supply Noise sensor. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2013	J	`jnl`	A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2013	Misc	`conf`	A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	B	`conf`	Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Effect-cause intra-cell diagnosis at transistor level. ISQED Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
2013	J	`jnl`	Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
2013	—	`conf`	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST. Asian Test Symposium Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2013	—	`conf`	On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	C	`conf`	SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	Test solution for data retention faults in low-power SRAMs. DATE Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	J	`jnl`	Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2013	—	`conf`	Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk. J. Electron. Test. Junxia Ma, Mohammad Tehranipoor, Patrick Girard
2012	Misc	`conf`	A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
2012	Misc	`conf`	Advanced test methods for SRAMs. VTS Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC J. Electron. Test. Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2012	B	`conf`	Coupling-based resistive-open defects in TAS-MRAM architectures. ETS Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	B	`conf`	Defect analysis in power mode control logic of low-power SRAMs. ETS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	C	`conf`	Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné
2012	—	`conf`	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	J	`jnl`	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2012	A	`conf`	Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	J	`jnl`	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns. J. Low Power Electron. Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen
2012	A	`conf`	Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	A	`conf`	On pinpoint capture power management in at-speed scan test generation. ITC Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2012	—	`conf`	Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka
2012	—	`conf`	Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot
2012	B	`conf`	Through-Silicon-Via resistive-open defect analysis. ETS Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2012	—	`conf`	Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	—	`conf`	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2011	C	`conf`	A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
2011	—	`conf`	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Neutron detection in atmospheric environment through static and dynamic SRAM-based test bench. LATW Luigi Dilillo, Paolo Rech, Jean-Marc Gallière, Patrick Girard, Frederic Wrobel, Frédéric Saigné
2011	—	`conf`	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch
2011	C	`conf`	On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011	A	`conf`	On using address scrambling to implement defect tolerance in SRAMs. ITC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
2011	Misc	`conf`	Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
2010	J	`jnl`	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
2010	J	`jnl`	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2010	—	`conf`	A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2010	—	`conf`	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
2010	A	`conf`	A roaming memory test bench for detecting particle induced SEUs. ITC Jean-Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo
2010	A*	`conf`	A statistical simulation method for reliability analysis of SRAM core-cells. DAC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	B	`conf`	A two-layer SPICE model of the ATMEL TSTAC ETS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2010	—	`conf`	An Exact and Efficient Critical Path Tracing Algorithm. DELTA Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2010	C	`conf`	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010	B	`conf`	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	Misc	`conf`	Detecting NBTI induced failures in SRAM core-cells. VTS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	J	`jnl`	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2010	—	`conf`	Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	A	`conf`	Is test power reduction through X-filling good enough? ITC Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2010	A	`conf`	Parity prediction synthesis for nano-electronic gate designs. ITC D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010	—	`conf`	Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric. ACM Great Lakes Symposium on VLSI Junxia Ma, Jeremy Lee, Mohammad Tehranipoor, Nisar Ahmed, Patrick Girard
2010	B	`conf`	Setting test conditions for improving SRAM reliability. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2009	J	`jnl`	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2009	—	`conf`	A case study on logic diagnosis for System-on-Chip. ISQED Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	A	`conf`	A new design-for-test technique for SRAM core-cell stability faults. DATE Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2009	C	`conf`	An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2009	J	`jnl`	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2009	C	`conf`	Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	—	`conf`	Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2009	J	`jnl`	Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2009	A	`conf`	NAND flash testing: A preliminary study on actual defects. ITC Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
2008	A	`conf`	A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	A	`conf`	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2008	J	`jnl`	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2008	Misc	`conf`	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin
2008	—	`conf`	CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor
2008	J	`jnl`	Guest Editorial. J. Electron. Test. Nicola Nicolici, Patrick Girard
2008	—	`conf`	Improving Diagnosis Resolution without Physical Information. DELTA Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	A	`conf`	Power-Aware Testing and Test Strategies for Low Power Devices. DATE Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen
2008	C	`conf`	SoC Symbolic Simulation: a case study on delay fault testing. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi
2008	A	`conf`	SoC Yield Improvement: Redundant Architectures to the Rescue? ITC Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	Using TMR Architectures for Yield Improvement. DFT Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	C	`conf`	A Mixed Approach for Unified Logic Diagnosis. DDECS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	A concurrent approach for testing address decoder faults in eFlash memories. ITC Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga
2007	A	`conf`	A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
2007	J	`jnl`	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	DERRIC: A Tool for Unified Logic Diagnosis. ETS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	B	`conf`	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	B	`conf`	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Fast Bridging Fault Diagnosis using Logic Information. ATS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
2007	Misc	`conf`	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	A	`conf`	Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2007	Misc	`conf`	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	J	`jnl`	A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	J	`jnl`	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2006	J	`jnl`	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2006	Misc	`conf`	An Overview of Failure Mechanisms in Embedded Flash Memories. VTS Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2006	C	`conf`	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2006	A	`conf`	Minimizing test power in SRAM through reduction of pre-charge activity. DATE Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
2006	—	`conf`	Power-Aware Test Data Compression for Embedded IP Cores. ATS Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault
2006	J	`jnl`	Reducing Power Dissipation in SRAM during Test. J. Low Power Electron. Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard
2006	C	`conf`	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich
2005	J	`jnl`	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2005	—	`conf`	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault
2005	Misc	`conf`	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	J	`jnl`	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2005	J	`jnl`	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan
2005	J	`jnl`	Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. J. Low Power Electron. Patrick Girard, Yannick Bonhomme
2005	B	`conf`	Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan
2005	A*	`conf`	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2005	C	`conf`	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault
2005	J	`jnl`	Welcome to the Journal of Low Power Electronics. J. Low Power Electron. Patrick Girard
2004	B	`conf`	An efficient scan tree design for test time reduction. ETS Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard
2004	C	`conf`	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	A	`conf`	Design of Routing-Constrained Low Power Scan Chains. DATE Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	—	`conf`	Design of Routing-Constrained Low Power Scan Chains. DELTA Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2004	B	`conf`	Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2004	—	`conf`	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	B	`conf`	Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	Misc	`conf`	March iC-: An Improved Version of March C- for ADOFs Detection. VTS Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2004	J	`jnl`	Power-Driven Routing-Constrained Scan Chain Design. J. Electron. Test. Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2004	—	`conf`	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan
2004	A	`conf`	SUIDT: safe user interface design tool. IUI Mickaël Baron, Patrick Girard
2003	J	`jnl`	A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electron. Test. Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
2003	—	`conf`	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri
2003	C	`conf`	Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2003	—	`conf`	Defect-oriented dynamic fault models for embedded-SRAMs. ETW Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2003	A	`conf`	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2003	—	`conf`	Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2002	J	`jnl`	Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	J	`jnl`	High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
2002	Misc	`conf`	On Using Efficient Test Sequences for BIST. VTS René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2002	A	`conf`	Power Driven Chaining of Flip-Flops in Scan Architectures. ITC Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2002	J	`jnl`	Survey of Low-Power Testing of VLSI Circuits. IEEE Des. Test Comput. Patrick Girard
2002	—	`conf`	Test Power: a Big Issue in Large SOC Designs. DELTA Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2001	Misc	`conf`	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2001	J	`jnl`	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2001	—	`conf`	End-User Programming in a Structured Dialogue Environment: the GIPSE Project. HCC Guillaume Patry, Patrick Girard
2001	—	`conf`	On hardware generation of random single input change test sequences. ETW René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2001	C	`conf`	Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
2000	—	`conf`	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2000	—	`conf`	Delay fault testing: choosing between random SIC and random MIC test sequences. ETW Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2000	Misc	`conf`	Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	—	`conf`	Low Power Testing of VLSI Circuits: Problems and Solutions. ISQED Patrick Girard
2000	A	`conf`	Low power BIST design by hypergraph partitioning: methodology and architectures. ITC Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch
1999	J	`jnl`	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1999	Misc	`conf`	A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch
1999	—	`conf`	GIPSE, A Model-Based System for CAD Software. CADUI Guillaume Patry, Patrick Girard
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	On calculating efficient LFSR seeds for built-in self test. ETW Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
1998	—	`conf`	A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
1998	—	`conf`	A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault
1997	A	`conf`	A gate resizing technique for high reduction in power consumption. ISLPED Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	J	`jnl`	A non-iterative gate resizing algorithm for high reduction in power consumption. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac
1997	Misc	`conf`	An optimized BIST test pattern generator for delay testing. VTS Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch
1997	A	`conf`	On Using Machine Learning for Logic BIST. ITC Christophe Fagot, Patrick Girard, Christian Landrault
1996	A	`conf`	A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1996	Misc	`conf`	A new test pattern generation method for delay fault testing. VTS S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1996	—	`conf`	DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. ED&TC P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	—	`conf`	A trace-based method for delay fault diagnosis in synchronous sequential circuits. ED&TC Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	J	`jnl`	An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electron. Test. Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1995	J	`jnl`	Delay fault diagnosis in sequential circuits based on path tracing. Integr. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1995	Misc	`conf`	Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez
1994	—	`conf`	Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1993	A	`conf`	An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	Misc	`conf`	A New Reliable Method for Delay-Fault Diagnosis. VLSI Design Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	A*	`conf`	A Novel Approach to Delay-Fault Diagnosis. DAC Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1992	J	`jnl`	Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Des. Test Comput. Patrick Girard, Christian Landrault, Serge Pravossoudovitch