Patrick Adde

22 papers B 1C 2Journal 9Unranked 10
YearRankTypeTitle / Venue / Authors
2012 — conf
A low-complexity soft-decision decoding architecture for the binary extended Golay code.
ICECS
Patrick Adde, Raphaël Le Bidan
2012 J jnl
Design of an Efficient Maximum Likelihood Soft Decoder for Systematic Short Block Codes.
IEEE Trans. Signal Process.
Patrick Adde, Daniel Gomez Toro, Christophe Jégo
2011 J jnl
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.
J. Signal Process. Syst.
Camille Leroux, Christophe Jégo, Patrick Adde, Deepak Gupta, Michel Jézéquel
2010 J jnl
A Turbo Decoder Included in a Multi-User Detector: A Solution to be Retained.
Int. J. Commun. Netw. Syst. Sci.
Sylvie Kerouédan, Makram Touzri, Patrick Adde, Samir Saoudi
2010 — conf
Design and implementation of a soft-decision decoder for Cortex codes.
ICECS
Patrick Adde, Christophe Jégo, Raphaël Le Bidan, Jorge Ernesto Pérez Chamorro
2009 J jnl
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
J. Signal Process. Syst.
Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
2008 — conf
A highly parallel Turbo Product Code decoder without interleaving resource.
SiPS
Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta
2008 — conf
On the higher efficiency of parallel Reed-Solomon turbo-decoding.
ICECS
Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
2008 J jnl
Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design.
EURASIP J. Wirel. Commun. Netw.
Raphaël Le Bidan, Camille Leroux, Christophe Jégo, Patrick Adde, Ramesh Pyndiah
2007 J jnl
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s.
Ann. des Télécommunications
Christophe Jégo, Patrick Adde, Camille Leroux
2007 — conf
Some Results on the Binary Minimum Distance of Reed-Solomon Codes and Block Turbo Codes.
ICC
Raphaël Le Bidan, Ramesh Pyndiah, Patrick Adde
2007 C conf
Towards Gb/s turbo decoding of product code onto an FPGA device.
ISCAS
Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel
2006 — conf
A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.
ISVLSI
Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
2006 — conf
Design, Implementation and Prototyping of a Flexible Architecture Dedicated to Block Turbo Decoding.
ReCoSoC
Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel
2006 C conf
Efficient architecture for Reed Solomon block turbo code.
ISCAS
Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel
2006 J jnl
Information Theory Turbo decoding of product codes for Gigabit per second applications and beyond.
Eur. Trans. Telecommun.
Javier Cuevas, Patrick Adde, Sylvie Kerouédan
2002 B conf
New architecture for high data rate turbo decoding of product codes.
GLOBECOM
Javier Cuevas, Patrick Adde, Sylvie Kerouédan, Ramesh Pyndiah
2001 — conf
Block turbo codes: towards implementation.
ICECS
Sylvie Kerouédan, Patrick Adde
2001 J jnl
How we implemented block turbo codes?
Ann. des Télécommunications
Sylvie Kerouédan, Patrick Adde, Ramesh Pyndiah
1999 J jnl
Design and performance of a product code turbo encoding-decoding prototype.
Ann. des Télécommunications
Patrick Adde, Ramesh Pyndiah, Fabien Buda
1996 — conf
Performance and complexity of block turbo decoder circuits.
ICECS
Patrick Adde, Ramesh Pyndiah, Olivier Raoul
1996 — conf
Turbo-decoder synchronisation procedure: application to the CAS5093 integrated circuit.
ICECS
Pascale Ferry, Patrick Adde, Gérard Graton