Pasquale Cocchini

14 papers A* 1A 3Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2024 J jnl
A Systematic Translation Validation Framework for MLIR-Based Compilers.
Int. J. Softw. Eng. Knowl. Eng.
Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang
2023 A conf
An Automated Verification Framework for HalideIR-Based Compiler Transformations.
DATE
Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang
2023 — conf
An Equivalence Checking Framework for Agile Hardware Design.
ASP-DAC
Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang
2023 J jnl
Towards A Correct-by-Construction FHE Model.
IACR Cryptol. ePrint Arch.
Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang
2022 A* conf
Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
DAC
Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
2021 J jnl
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.
CoRR
Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang
2021 J jnl
RHNAS: Realizable Hardware and Neural Architecture Search.
CoRR
Yash Akhauri, Adithya Niranjan, J. Pablo Muñoz, Suvadeep Banerjee, Abhijit Davare, Pasquale Cocchini, Anton A. Sorokin, Ravi Iyer, Nilesh Jain
2004 J jnl
Repeater scaling and its impact on CAD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
2003 J jnl
A methodology for optimal repeater insertion in pipelined interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pasquale Cocchini
2003 — conf
The scaling challenge: can correct-by-construction design help?
ISPD
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
2002 A conf
Concurrent flip-flop and repeater insertion for high performance integrated circuits.
ICCAD
Pasquale Cocchini
2000 J jnl
Fanout optimization using bipolar LT-trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pasquale Cocchini, Massoud Pedram
1998 A conf
Fanout optimization under a submicron transistor-level delay model.
ICCAD
Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
1997 J jnl
A comprehensive submicrometer MOST delay model and its application to CMOS buffers.
IEEE J. Solid State Circuits
Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni