Pascal Witte

15 papers C 5Journal 4Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
A Low-Distortion Adderless Zero-Time Reset Incremental Delta-Sigma Analog-to-Digital Converter.
PRIME
Jesko Flemming, Kaxin Tang, Bernhard Wicht, Pascal Witte
2025 — conf
A Spur-Reduced Power-Efficient Fully Differential VCO-based Operational Transconductance Amplifier.
PRIME
Kaxin Tang, Jesko Flemming, Hendrik Siemssen, Pascal Witte, Bernhard Wicht
2024 C conf
A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs.
ISCAS
Jesko Flemming, Bernhard Wicht, Pascal Witte
2024 — conf
A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs.
SMACD
Jesko Flemming, Timon Rogge, Bernhard Wicht, Pascal Witte
2023 C conf
A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs.
ISCAS
Jesko Flemming, Bernhard Wicht, Pascal Witte
2023 — conf
Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures.
SMACD
Jesko Flemming, Bernhard Wicht, Pascal Witte
2014 J jnl
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW.
IEEE J. Solid State Circuits
John G. Kauffman, Pascal Witte, Matthias Lehmann, Joachim Becker, Yiannos Manoli, Maurits Ortmanns
2012 — conf
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW.
ISSCC
Pascal Witte, John G. Kauffman, Joachim Becker, Yiannos Manoli, Maurits Ortmanns
2012 C conf
An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal.
ISCAS
Pascal Witte, John G. Kauffman, Timon Brückner, Joachim Becker, Maurits Ortmanns
2011 J jnl
A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs.
IEEE Trans. Circuits Syst. II Express Briefs
Pascal Witte, John G. Kauffman, Joachim Becker, Maurits Ortmanns
2011 J jnl
An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.
IEEE J. Solid State Circuits
John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns
2011 — conf
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization.
ISSCC
John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns
2010 J jnl
Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pascal Witte, Maurits Ortmanns
2010 C conf
Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs.
ISCAS
Pascal Witte, Carsten Noeske, Maurits Ortmanns
2009 C conf
A Background DAC Error Estimation in Sigma-Delta ADCs using a Pseudo Random Noise based Correlation Technique.
ISCAS
Pascal Witte, Maurits Ortmanns