Pascal Vivet - RankMe

108 papers A* 1A 19B 4C 7Misc 2Journal 18Unranked 55

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Event-based Audio Prediction with Spectro-Temporal Event-Graphs. ISCAS Lars Rafeldt, Thomas Mesquida, Hiroshi Nakano, Manon Dampfhoffer, Filippo Moro, Pascal Vivet, Melika Payvand, Thomas Dalgaty
2025	C	`conf`	Exploring Enhancements to 1T1C FeMFET Bitcells with a Versatile DTCO Methodology. VLSI-SoC Rosario Pronsat, Antoine Cauquil, Pascal Vivet, Jean Coignus, Damien Deleruyelle, Cédric Marchand, Lioua Labrak, Ian O'Connor
2025	A*	`conf`	Graph Neural Network Combining Event Stream and Periodic Aggregation for Low-Latency Event-based Vision. CVPR Manon Dampfhoffer, Thomas Mesquida, Damien Joubert, Thomas Dalgaty, Pascal Vivet, Christoph Posch
2025	A	`conf`	J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor. ISLPED Benoît Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jérôme Chossat, Pascal Pierunek, Pascal Vivet, Sébastien Thuries
2025	J	`jnl`	J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor. CoRR Benoît Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jérôme Chossat, Pascal Pierunek, Pascal Vivet, Sébastien Thuries
2023	A	`conf`	G2N2: Lightweight Event Stream Classification with GRU Graph Neural Networks. BMVC Thomas Mesquida, Manon Dampfhoffer, Thomas Dalgaty, Pascal Vivet, Amos Sironi, Christoph Posch
2023	—	`conf`	HUGNet: Hemi-Spherical Update Graph Neural Network applied to low-latency event-based optical flow. CVPR Workshops Thomas Dalgaty, Thomas Mesquida, Damien Joubert, Amos Sironi, Pascal Vivet, Christoph Posch
2023	A	`conf`	The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks. DATE Thomas Dalgaty, Thomas Mesquida, Damien Joubert, Amos Sironi, Cyrille Soubeyrat, Pascal Vivet, Christoph Posch
2022	J	`jnl`	Architecting Optically Controlled Phase Change Memory. ACM Trans. Archit. Code Optim. Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun, Ajay Joshi
2021	J	`jnl`	Architecting Optically-Controlled Phase Change Memory. CoRR Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun, Ajay Joshi
2021	J	`jnl`	IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2021	J	`jnl`	PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ayse K. Coskun
2020	—	`conf`	2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm ISSCC Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy
2020	A	`conf`	Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing. DATE Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud
2020	A	`conf`	M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. DATE Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard
2020	A	`conf`	POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems. DATE Yvain Thonnart, Stéphane Bernabé, Jean Charbonnier, Christian Bernard, David Coriat, César Fuguet Tortolero, Pierre Tissier, Benoît Charbonnier, Stéphane Malhouitre, Damien Saint-Patrice, Myriam Assous, Aditya Narayan, Ayse K. Coskun, Denis Dutoit, Pascal Vivet
2020	A	`conf`	Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization. ISLPED Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles
2020	A	`conf`	System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive Applications. DATE Aditya Narayan, Yvain Thonnart, Pascal Vivet, Ajay Joshi, Ayse K. Coskun
2019	—	`conf`	A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC Tony F. Wu, Binh Q. Le, Robert M. Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra
2019	A	`conf`	Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. DATE Pascal Vivet, Gilles Sicard, Laurent Millet, Stéphane Chevobbe, Karim Ben Chehida, Luis Angel Cubero, Monte Alegre, Maxence Bouvier, Alexandre Valentian, Maria Lepecq, Thomas Dombek, Olivier Bichler, Sébastien Thuries, Didier Lattard, Séverine Cheramy, Perrine Batude, Fabien Clermidy
2019	—	`conf`	Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone. ASYNC Yvain Thonnart, Pascal Vivet, Shikhanshu Agarwal, Ramesh Chauhan
2019	C	`conf`	Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. VLSI-SoC Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles
2019	—	`conf`	Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 3DIC Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet
2019	—	`conf`	Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2019	—	`conf`	RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
2019	B	`conf`	Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné
2019	A	`conf`	WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs. DATE Aditya Narayan, Yvain Thonnart, Pascal Vivet, César Fuguet Tortolero, Ayse K. Coskun
2018	—	`conf`	A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet
2018	B	`conf`	BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2018	—	`conf`	Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
2017	J	`jnl`	A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
2017	—	`conf`	Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné
2016	—	`conf`	8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
2016	J	`jnl`	Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Des. Test Perceval Coudrain, Papa Momar Souare, Rafael Prieto, Vincent Fiori, Alexis Farcy, Laurent Le Pailleur, Jean-Philippe Colonna, Cristiano Santos, Pascal Vivet, M. Haykel Ben Jamaa, Denis Dutoit, François de Crecy, Sylvain Dumas, Christian Chancel, Didier Lattard, Séverine Cheramy
2016	J	`jnl`	Guest Editors' Introduction: Robust 3-D Stacked ICs. IEEE Des. Test S. Saqib Khursheed, Pascal Vivet, Fabian Hopsch, Erik Jan Marinissen
2016	B	`conf`	IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. ETS Jean Durupt, Pascal Vivet, Juergen Schloeffel
2016	—	`conf`	ITAC: A complete 3D integration test platform. 3DIC Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, Gaël Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy
2016	J	`jnl`	Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini
2016	—	`conf`	Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes. 3DIC Cristiano Santos, Pascal Vivet, Sébastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, Lee Wang
2015	—	`conf`	3D DFT Challenges and Solutions. ISVLSI Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel
2015	—	`conf`	3D ICs: An opportunity for fully-integrated, dense and efficient power supplies. 3DIC Gaël Pillonnet, Nicolas Jeanniot, Pascal Vivet
2015	—	`conf`	3D advanced integration technology for heterogeneous systems. 3DIC Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy
2015	A	`conf`	A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures. ISLPED Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Julien Mottin, Pascal Vivet, Hela Boussetta, Nicolas Peltier
2015	C	`conf`	Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
2015	—	`conf`	Graphite-based heat spreaders for hotspot mitigation in 3D ICs. 3DIC Cristiano Santos, Rafael Prieto, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Reis
2015	—	`conf`	Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy
2015	—	`conf`	Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller. NEWCAS Florent Berthier, Edith Beigné, Pascal Vivet, Olivier Sentieys
2015	A	`conf`	Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. DATE Christian Weis, Matthias Jung, Peter Ehses, Cristiano Santos, Pascal Vivet, Sven Goossens, Martijn Koedam, Norbert Wehn
2015	—	`conf`	Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. ISVLSI Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson
2015	—	`conf`	Two-phase protocol converters for 3D asynchronous 1-of-n data links. ASP-DAC Julian J. H. Pontes, Pascal Vivet, Yvain Thonnart
2014	—	`conf`	2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2014	A	`conf`	Early design stage thermal evaluation and mitigation: The locomotiv architectural case. DATE Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier
2014	—	`ed.`	Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014 INA-OCMC@HiPEAC Giorgos Dimitrakopoulos, Sören Sonntag, José Flich, Pascal Vivet
2014	Misc	`conf`	The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators. CASES Bilel Belhadj, Alexandre Valentian, Pascal Vivet, Marc Duranton, Liqiang He, Olivier Temam
2014	A	`conf`	Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip. DATE Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Denis Dutoit, Luca Benini
2014	—	`conf`	Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit. ICECS Cristiano Santos, Pascal Vivet, Ricardo Augusto da Luz Reis
2014	—	`conf`	Thermal modeling methodology for efficient system-level thermal analysis. CICC Cristiano Santos, Pascal Vivet, Gene Matter, Nicolas Peltier, Sylvian Kaiser, Ricardo Augusto da Luz Reis
2014	—	`conf`	Thermal performance of 3D ICs: Analysis and alternatives. 3DIC Cristiano Santos, Pascal Vivet, Jean-Philippe Colonna, Perceval Coudrain, Ricardo Augusto da Luz Reis
2014	—	`conf`	Using TSVs for thermal mitigation in 3D circuits: Wish and truth. 3DIC Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy
2013	C	`conf`	3D stacking for multi-core architectures: From WIDEIO to distributed caches. ISCAS Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Pascal Vivet
2013	—	`conf`	A 3D IC BIST for pre-bond test of TSVs using ring oscillators. NEWCAS Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale
2013	—	`conf`	A dynamic stream link for efficient data flow control in NoC based heterogeneous MPSoC. ASP-DAC Claude Helmstetter, Sylvain Basset, Romain Lemaire, Fabien Clermidy, Pascal Vivet, Michel Langevin, Chuck Pilkington, Pierre G. Paulin, Didier Fuin
2013	—	`conf`	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
2013	—	`conf`	A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	A	`conf`	Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. DATE Alex Yakovlev, Pascal Vivet, Marc Renaudin
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	A	`conf`	Fast and accurate TLM simulations using temporal decoupling for FIFO-based communications. DATE Claude Helmstetter, Jérôme Cornet, Bruno Galilée, Matthieu Moy, Pascal Vivet
2013	—	`conf`	Fast and accurate power annotated simulation: Application to a many-core architecture. PATMOS Thomas Ducroux, Germain Haugou, Vincent Risson, Pascal Vivet
2013	—	`conf`	H2A: A hardened asynchronous network on chip. SBCCI Julian J. H. Pontes, Ney Calazans, Pascal Vivet
2013	C	`conf`	Parity check for m-of-n delay insensitive codes. IOLTS Julian J. H. Pontes, Ney Calazans, Pascal Vivet
2013	—	`conf`	System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit. 3DIC Cristiano Santos, Pascal Vivet, Denis Dutoit, Philippe Garrault, Nicolas Peltier, Ricardo Reis
2012	—	`ed.`	18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012 ASYNC Jens Sparsø, Montek Singh, Pascal Vivet
2012	—	`conf`	A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2012	—	`conf`	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. ASYNC Julian J. H. Pontes, Ney Calazans, Pascal Vivet
2012	A	`conf`	An accurate Single Event Effect digital design flow for reliable system level design. DATE Julian J. H. Pontes, Ney Calazans, Pascal Vivet
2011	A	`conf`	3D Embedded multi-core: Some perspectives. DATE Fabien Clermidy, Florian Darve, Denis Dutoit, Walid Lafi, Pascal Vivet
2011	C	`conf`	3D NoC using through silicon Via: An asynchronous implementation. VLSI-SoC Pascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy
2011	J	`jnl`	Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq
2011	J	`jnl`	Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems. IEEE Des. Test Comput. Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet
2011	Misc	`conf`	Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends. CODES+ISSS Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, Drew Wingard
2011	J	`jnl`	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2011	—	`conf`	Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links. ISVLSI Florian Darve, Abbas Sheibanyrad, Pascal Vivet, Frédéric Pétrot
2010	—	`conf`	A 477mW NoC-based digital baseband for MIMO 4G SDR. ISSCC Fabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn
2010	A	`conf`	A fully-asynchronous low-power framework for GALS NoC integration. DATE Yvain Thonnart, Pascal Vivet, Fabien Clermidy
2010	—	`conf`	Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems. ASYNC Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Nicolas Leblond, Pascal Vivet, G. Waltisperger, Jérôme Willemin
2010	—	`conf`	On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2009	—	`conf`	A Communication and configuration controller for NoC based reconfigurable data flow architecture. NOCS Fabien Clermidy, Romain Lemaire, Yvain Thonnart, Pascal Vivet
2009	J	`jnl`	An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
2009	—	`conf`	Design and Implementation of a GALS Adapter for ANoC Based Architectures. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2009	J	`jnl`	Power Reduction of Asynchronous Logic Circuits Using Activity Detection. IEEE Trans. Very Large Scale Integr. Syst. Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	J	`jnl`	A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens
2008	—	`conf`	A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. ESSCIRC Edith Beigné, Fabien Clermidy, Sylvain Miermont, Alexandre Valentian, Pascal Vivet, S. Barasinski, F. Blisson, N. Kohli, S. Kumar
2008	—	`conf`	Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. ASYNC Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	—	`conf`	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. NOCS Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet
2008	—	`conf`	Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner
2008	—	`conf`	Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. ISVLSI Hugo Lebreton, Pascal Vivet
2007	—	`conf`	A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS Sylvain Miermont, Pascal Vivet, Marc Renaudin
2007	—	`conf`	A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens
2007	—	`conf`	A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation. RIVF Anh-Vu Dinh-Duc, Pascal Vivet, Alain Clouard
2007	—	`conf`	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
2007	—	`conf`	Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip. ASYNC Gwen Salaün, Wendelin Serwe, Yvain Thonnart, Pascal Vivet
2007	J	`jnl`	Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. IEEE Des. Test Comput. Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet
2006	—	`conf`	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. ASYNC Edith Beigné, Pascal Vivet
2005	—	`conf`	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
2001	J	`jnl`	A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE J. Solid State Circuits André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet
1999	—	`conf`	A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC Marc Renaudin, Pascal Vivet, Frédéric Robin
1998	—	`conf`	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC Marc Renaudin, Pascal Vivet, Frédéric Robin