Pascal Meinerzhagen

16 papers A 2C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'24).
IEEE Des. Test
Pascal Meinerzhagen, Kapil Dev, Jerald Yoo
2024 J jnl
ISLPED 2023: International Symposium on Low-Power Electronics and Design.
IEEE Des. Test
Axel Jantsch, Swaroop Ghosh, Ümit Y. Ogras, Pascal Meinerzhagen
2024 A ed.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2024, Newport Beach, CA, USA, August 5-7, 2024
ISLPED
Pascal Meinerzhagen, Kapil Dev, Jerald Yoo
2023 — conf
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS.
VLSI Technology and Circuits
Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
2020 A conf
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization.
ITC
Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang
2019 — conf
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop.
ESSCIRC
Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018 — conf
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
ISSCC
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2017 J jnl
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Robert Giterman, Adam Teman, Pascal Meinerzhagen
2016 J jnl
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
2016 C conf
A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design.
ISCAS
Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
2016 J jnl
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement.
ACM Trans. Design Autom. Electr. Syst.
Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
2016 J jnl
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish
2016 J jnl
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
2013 — conf
A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
NEWCAS
Ibrahim Kazi, Pascal Meinerzhagen, Pierre-Emmanuel Gaillardon, Davide Sacchetto, Andreas Burg, Giovanni De Micheli
2013 — conf
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS.
ESSCIRC
Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues
2012 — conf
Replica bit-line technique for embedded multilevel gain-cell DRAM.
NEWCAS
Muhammad Umer Khalid, Pascal Meinerzhagen, Andreas Burg