Partha Biswas

15 papers A* 1A 3B 1Misc 3Journal 6Unranked 1
YearRankTypeTitle / Venue / Authors
2025 B conf
DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing.
LCTES
Abhinav Kumar, Atharva Khedkar, Hwisoo So, Megan Kuo, Ameya Gurjar, Partha Biswas, Aviral Shrivastava
2022 J jnl
Identification of blood-based inflammatory biomarkers for the early-stage detection of acute myocardial infarction.
Netw. Model. Anal. Health Informatics Bioinform.
Md. Takim Sarker, Shuvo Saha, Partha Biswas, Md Tanvir Islam, Mohammad Ashik Sheikh, Md. Nahid Hasan, Nadira Islam, Md. Mobenul Islam Rabbe, Md. Oliullah Rafi
2008 Misc conf
Comprehensive isomorphic subtree enumeration.
CASES
Partha Biswas, Girish Venkataramani
2007 J jnl
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007 J jnl
Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2006 A conf
Automatic identification of application-specific functional units with architecturally visible storage.
DATE
Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006 J jnl
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).
ACM Trans. Design Autom. Electr. Syst.
Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau
2006 J jnl
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. Very Large Scale Integr. Syst.
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2006 Misc conf
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2005 J jnl
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.
IEEE Trans. Computers
Partha Biswas, Nikil D. Dutt
2005 A conf
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2004 A* conf
Introduction of local memory elements in instruction set extensions.
DAC
Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
2003 Misc conf
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.
CASES
Partha Biswas, Nikil D. Dutt
2002 — conf
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
ISSS
Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi
2002 A conf
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
DATE
Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau