Parth Parekh

17 papers Journal 9Unranked 8
YearRankTypeTitle / Venue / Authors
2025 J jnl
Deep Parenchymal Steatosis Assessment and Quantification in Histopathology.
IEEE Access
Rishit Gupta, Amit Nagora, Phidakordor Sahshong, Parth Parekh, Apurba Chakraborty, Manish Bhatt
2023 J jnl
Bi-Directional Gated Ring Oscillator Time Integrator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fei Yuan, Parth Parekh, Yushi Zhou
2023 J jnl
Underwater Robotics Semantic Parser Assistant.
CoRR
Parth Parekh, Cedric McGuire, Jake Imyak
2022 — conf
All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing.
NEWCAS
Parth Parekh, Fei Yuan, Yushi Zhou
2022 — conf
Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing.
MWSCAS
Parth Parekh, Fei Yuan, Yushi Zhou
2022 J jnl
Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter.
Microelectron. J.
Parth Parekh, Fei Yuan, Yushi Zhou
2022 J jnl
Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Parth Parekh, Fei Yuan, Yushi Zhou
2021 — conf
Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing.
MWSCAS
Parth Parekh, Fei Yuan, Yushi Zhou
2020 — conf
All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line.
MWSCAS
Parth Parekh, Fei Yuan, Yushi Zhou
2020 J jnl
Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs
Fei Yuan, Parth Parekh
2020 — conf
Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability.
MWSCAS
Parth Parekh, Fei Yuan, Yushi Zhou
2020 J jnl
Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator.
IET Circuits Devices Syst.
Fei Yuan, Parth Parekh
2019 — conf
All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator.
MWSCAS
Fei Yuan, Parth Parekh
2019 — conf
Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration.
MWSCAS
Fei Yuan, Parth Parekh
2018 J jnl
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator.
Microelectron. J.
Young Jun Park, Parth Parekh, Fei Yuan
2018 — conf
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator.
NEWCAS
Parth Parekh, Fei Yuan
2016 J jnl
A Bayesian Ensemble for Unsupervised Anomaly Detection.
CoRR
Edward Yu, Parth Parekh
2025 Best paper conf
Assessing the Effectiveness of the Tigress Obfuscator Against MOPSA and BinaryNinja.
CheckMATE
Nicolò Altamura, Enrico Bragastini, Marco Campion, Mila Dalla Preda
2026 Best paper preprint
ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage.
arXiv
Chang Liu, Noah Fleischmann, Nicolò Altamura, Edward Raff, James Holt, Kristopher Micinski