Parag Upadhyaya

34 papers C 2Journal 9Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Adaptive Wavelength Tracking and Temperature Tuning of A 45Gbps Coupled Ring Resonator Based DWDM Link. OFC Zhaowen Wang, Ade Bekele, Mingshan Li, Mayank Raj, Chuan Xie, Anish Joshi, Gareeyasee Saha, Zakriya Mohammed, Stuart Daudlin, Parag Upadhyaya, Yohan Frans
2024	—	`conf`	A 64 Gb/s NRZ O-Band Ring Modulator with 3.2 THz FSR for DWDM Applications. OFC Chuan Xie, Mayank Raj, Anish Joshi, Zakriya Mohammed, Gareeyasee Saha, Zhaowen Wang, Parag Upadhyaya, Yohan Frans
2023	—	`conf`	A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. ISSCC Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans
2022	J	`jnl`	A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. IEEE J. Solid State Circuits Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans
2021	—	`conf`	A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. VLSI Circuits Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang, Ying Cao, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans
2019	J	`jnl`	A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. IEEE J. Solid State Circuits Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang
2018	—	`conf`	A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. VLSI Circuits Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang
2018	—	`conf`	A 112-GB/S PAM4 Transmitter in 16NM FinFET. VLSI Circuits Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang
2018	—	`conf`	A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. VLSI Circuits James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang
2018	—	`conf`	A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. ISSCC Didem Turker, Ade Bekele, Parag Upadhyaya, Bob Verbruggen, Ying Cao, Shaojun Ma, Christophe Erdmann, Brendan Farley, Yohan Frans, Ken Chang
2018	—	`conf`	A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. ISSCC Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang
2017	—	`conf`	6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. ISSCC Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang
2017	J	`jnl`	A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET. IEEE J. Solid State Circuits Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang
2017	J	`jnl`	A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS. IEEE J. Solid State Circuits Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang
2017	J	`jnl`	A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. IEEE J. Solid State Circuits Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang
2017	J	`jnl`	A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. IEEE J. Solid State Circuits Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, Vassili Kireev, Mohamed Elzeftawi, Hiva Hedayati, Toan Pham, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang
2016	—	`conf`	3.7 A 40-to-64Gb/s NRZ transmitter with supply-regulated front-end in 16nm FinFET. ISSCC Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang
2016	—	`conf`	A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. ESSCIRC Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang
2016	—	`conf`	A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS. A-SSCC Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang
2016	J	`jnl`	A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET. IEEE J. Solid State Circuits Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang
2016	—	`conf`	A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. VLSI Circuits Yohan Frans, Mohamed Elzeftawi, Hiva Hedayati, Jay Im, Vassili Kireev, Toan Pham, Jaewook Shin, Parag Upadhyaya, Lei Zhou, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang, Ken Chang
2016	—	`conf`	A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET. VLSI Circuits Mayank Raj, Parag Upadhyaya, Yohan Frans, Ken Chang
2016	—	`conf`	A fully-adaptive wideband 0.5-32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. VLSI Circuits Parag Upadhyaya, Ade Bekele, Didem Turker Melek, Haibing Zhao, Jay Im, Junho Cho, Kee Hian Tan, Scott McLeod, Stanley Chen, Wenfeng Zhang, Yohan Frans, Ken Chang
2015	—	`conf`	3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS. ISSCC Parag Upadhyaya, Jafar Savoj, Fu-Tai An, Ade Bekele, Anup P. Jose, Bruce Xu, Zhaoyin Daniel Wu, Didem Turker, Hesam Amir Aslanzadeh, Hiva Hedayati, Jay Im, Siok-Wei Lim, Stanley Chen, Toan Pham, Yohan Frans, Ken Chang
2015	J	`jnl`	A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS. IEEE J. Solid State Circuits Yohan Frans, Declan Carey, Marc Erett, Hesam Amir Aslanzadeh, Wayne Y. Fang, Didem Turker, Anup P. Jose, Adebabay Bekele, Jay Im, Parag Upadhyaya, Zhaoyin Daniel Wu, Kenny C.-H. Hsieh, Jafar Savoj, Ken Chang
2014	—	`conf`	2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. ISSCC Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang
2014	—	`conf`	Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS. CICC Jafar Savoj, Hesam Amir Aslanzadeh, Declan Carey, Marc Erett, Wayne Fang, Yohan Frans, Kenny C.-H. Hsieh, Jay Im, Anup P. Jose, Didem Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2013	J	`jnl`	A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs. IEEE J. Solid State Circuits Jafar Savoj, Kenny C.-H. Hsieh, Fu-Tai An, J. Gong, Jay Im, Xuewen Jiang, Anup P. Jose, Vassili Kireev, Siok-Wei Lim, Arianne Roldan, D. Z. Turker, Parag Upadhyaya, Zhaoyin Daniel Wu, Ken Chang
2012	—	`conf`	A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS. VLSIC Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Ade Bekele, Stanley Chen, Xuewen Jiang, Kang Wei Lai, Chi Fung Poon, Aman Sewani, Didem Turker, Karthik Venna, Zhaoyin Daniel Wu, Bruce Xu, Elad Alon, Ken Chang
2012	—	`conf`	Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. CICC Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang
2012	—	`conf`	Spin wave nanofabric update. NANOARCH J. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, Kin Wong, S. Cherepov, P. Khalili Amiri, Kang L. Wang, J. Hockel, A. Bur, Gregory P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y.-J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, Alexander Khitun
2006	C	`conf`	A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor. ISCAS Le Wang, Parag Upadhyaya, Pinping Sun, Yang Zhang, Deuk Hyoun Heo, Yi-Jan Emery Chen, DongHo Jeong
2006	C	`conf`	Enhanced gm3 cancellation for linearity improvement in CMOS LNAs. ISCAS Mallesh Rajashekharaiah, Parag Upadhyaya, Deuk Hyoun Heo
2005	—	`conf`	A new gain controllable on-chip active balun for 5 GHz direct conversion receiver. ISCAS (5) Mallesh Rajashekharaiah, Parag Upadhyaya, Deuk Hyoun Heo, Yi-Jan Emery Chen