Parag K. Lala - RankMe

67 papers A 7C 2Misc 4Journal 27Unranked 26

Year	Rank	Type	Title / Venue / Authors
2010	—	`conf`	A Quantum Key Distribution Protocol. Security and Management Parag K. Lala
2010	J	`jnl`	An Approach for Implementing State Machines with Online Testability. VLSI Design Parag K. Lala, Adam Mathews, James Patrick Parkerson
2008	—	`book`	An Introduction to Logic Circuit Testing Parag K. Lala
2008	—	`conf`	On FPGA Design with Self-checking and Fault Tolerance Capability. ERSA Parag K. Lala
2007	J	`jnl`	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems. J. Electron. Test. Jia Di, Parag K. Lala
2007	J	`jnl`	Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding. IEEE Trans. Circuits Syst. I Regul. Pap. Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2006	J	`jnl`	On self-healing digital system design. Microelectron. J. Parag K. Lala, B. Kiran Kumar, James Patrick Parkerson
2006	J	`jnl`	Reversible-logic design with online testability. IEEE Trans. Instrum. Meas. Dilip P. Vasudevan, Parag K. Lala, Jia Di, James Patrick Parkerson
2005	—	`conf`	A Technique for Designing Totally Self-Checking Domino Logic Circuits. ISQED C. K. Tang, Parag K. Lala, James Patrick Parkerson
2005	—	`conf`	A Technique for Modular Design of Self-Checking Carry-Select Adder. DFT Dilip P. Vasudevan, Parag K. Lala
2005	—	`conf`	CMOS Realization of Online Testable Reversible Logic Gates. ISVLSI Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2005	—	`conf`	On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits. DFT Jia Di, Parag K. Lala, Dilip P. Vasudevan
2004	—	`conf`	A New Reversible Logic Gate and its Applications. ESA/VLSI Dilip P. Vasudevan, Parag K. Lala
2004	—	`conf`	A Novel Approach for On-line Testable Reversible Logic Circuit Desig. Asian Test Symposium Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2004	—	`conf`	Logic implementation using a reversible gate. Circuits, Signals, and Systems Dilip P. Vasudevan, James Patrick Parkerson, Parag K. Lala
2004	—	`conf`	Online Testable Reversible Logic Circuit Design using NAND Blocks. DFT Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson
2003	—	`conf`	A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems. DFT Parag K. Lala
2003	J	`jnl`	An Architecture for Self-Healing Digital Systems. J. Electron. Test. Parag K. Lala, B. Kiran Kumar
2003	A	`conf`	An FPGA architecture with built-in error correction capability. FPGA Parag K. Lala, B. Kiran Kumar
2003	A	`conf`	Fault Injection for Verifying Testability at the VHDL Level. ITC S. R. Seward, Parag K. Lala
2003	C	`conf`	Fault Injection in Digital Logic Circuits at the VHDL Level. IOLTS S. R. Seward, Parag K. Lala
2003	C	`conf`	On-Line Error Detecting Constant Delay Adder. IOLTS Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala
2003	A	`conf`	On-line Detection of Faults in Carry-Select Adders. ITC B. Kiran Kumar, Parag K. Lala
2003	J	`jnl`	Self-checking logic design for FPGA implementation. IEEE Trans. Instrum. Meas. Parag K. Lala, Alfred L. Burress
2002	—	`conf`	An Architecture for Self-Healing Digital Systems. IOLTW Parag K. Lala, B. Kiran Kumar
2002	—	`conf`	Human Immune System Inspired Architecture for Self-Healing Digital Systems. ISQED Parag K. Lala, B. Kiran Kumar
2002	—	`conf`	On Biologically-Inspired Design of Fault-Tolerant Digital Systems. DELTA Parag K. Lala, K. K. Bondali
2002	—	`conf`	On-line Error Detection in a Carry-free Adder. IWLS Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala
2001	J	`jnl`	A Fine Grain Configurable Logic Block for Self-checking FPGAs. VLSI Design Parag K. Lala, Alvernon Walker
2001	—	`conf`	A Unified Scheme for Designing Testable State Machines. Asian Test Symposium Parag K. Lala, Alvernon Walker
2001	—	`conf`	An Approach for Designing On-Line Testable State Machines. IOLTW Parag K. Lala, Mark G. Karpovsky
2001	—	`conf`	On-Line Error Detectable Carry-Free Adder Design. DFT Parag K. Lala, Alvernon Walker
2000	—	`conf`	A Transition Based BIST Approach for Passive Analog Circuits. ISQED Alvernon Walker, Parag K. Lala
2000	—	`conf`	An On-Line Reconfigurable FPGA Architecture. DFT Parag K. Lala, Alvernon Walker
2000	—	`conf`	Fault Analysis of the Multiple Valued Logic Using Spectral Method. ISMVL Jong O. Kim, Parag K. Lala, Young Gun Kim, Heung-Soo Kim
2000	J	`jnl`	Guest Editorial. VLSI Design Parag K. Lala
1999	—	`conf`	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. DFT Parag K. Lala, Anup Singh, Alvernon Walker
1999	—	`conf`	A technique for designing self-checking logic for FPGAs. ISCAS (1) Parag K. Lala, Alfred L. Burress
1999	A	`conf`	Self-Checking Logic Design for LUT-Based FPGAs. FPGA Parag K. Lala, Alfred L. Burress
1998	J	`jnl`	Guest Editorial. VLSI Design Parag K. Lala
1998	J	`jnl`	On Self-Checking Design of CMOS Circuits for Multiple Faults. VLSI Design Fadi Busaba, Parag K. Lala, Alvernon Walker
1997	—	`conf`	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring. DFT Alvernon Walker, Algernon P. Henry, Parag K. Lala
1997	A	`conf`	On-Line Testable Logic Desgin for FPGA Implementation. ITC Alfred L. Burress, Parag K. Lala
1996	—	`conf`	A unified approach for off-line and on-line testing of VLSI systems. DFT Parag K. Lala, S. Yang, Fadi Busaba
1996	J	`jnl`	Modular implementation of efficient self-checking checkers for the Berger code. J. Electron. Test. D. A. Pierce, Parag K. Lala
1996	J	`jnl`	Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. IEEE Trans. Computers K. Lai, Parag K. Lala
1995	—	`conf`	A graph coloring based approach for self-checking logic circuit design. Asian Test Symposium Fadi Y. Busaba, Parag K. Lala
1994	J	`jnl`	An Approach for Self-Checking Realization of Interacting Finite State Machines. VLSI Design Fadi Busaba, Parag K. Lala
1994	J	`jnl`	Partially Strongly Fault Secure and Partially Strongly Code Disjoint I-out-of-3 Code Checker. IEEE Trans. Computers J. Q. Wang, Parag K. Lala
1994	J	`jnl`	Self-checking combinational circuit design for single and unidirectional multibit error. J. Electron. Test. Fadi Y. Busaba, Parag K. Lala
1994	J	`jnl`	Techniques for Self-Checking Combinational Logic Synthesis. VLSI Design Fadi Busaba, Parag K. Lala
1993	Misc	`conf`	Input and output encoding techniques for on-line error detection in combinational logic circuits. VTS Fadi Y. Busaba, Parag K. Lala
1992	J	`jnl`	A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. IEEE Trans. Computers Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala
1992	Misc	`conf`	A concurrent checking scheme for single and multibit errors in logic circuits. VTS B. Kolla, Parag K. Lala, K. C. Yarlagadda
1992	Misc	`conf`	A new technique for totally self-checking CMOS circuit design for stuck-on and stuck-off faults. VTS Manjit S. Cheema, Parag K. Lala
1992	J	`jnl`	Fault Diagnosis in Analog Circuits Using Element Modulation. IEEE Des. Test Comput. Alvernon Walker, Winser E. Alexander, Parag K. Lala
1992	J	`jnl`	Totally self-checking CMOS circuit design for breaks and stuck-on faults. IEEE J. Solid State Circuits Manjit S. Cheema, Parag K. Lala
1991	J	`jnl`	A Note on t-EC/d-UED Codes. IEEE Trans. Computers Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala
1991	Misc	`conf`	An approach for designing self-checking logic using residue codes. VTS Parag K. Lala, Fadi Y. Busaba, K. C. Yarlagadda
1990	J	`jnl`	A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips. Microprocessing and Microprogramming Parag K. Lala
1988	J	`jnl`	A MOS implementation of totally self-checking checker for the 1-out-of-3 code. IEEE J. Solid State Circuits Dali L. Tao, Parag K. Lala, Carlos R. P. Hartmann
1988	J	`jnl`	An efficient class of unidirectional error detecting/correcting codes. IEEE Trans. Computers Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala
1986	A	`conf`	A Concurrent Testing Strategy for PLAs. ITC Dali L. Tao, Carlos R. P. Hartmann, Parag K. Lala
1986	A	`conf`	On Built-In Testing of VLSI Chips. ITC Parag K. Lala
1985	J	`jnl`	Fault tolerance and self-checking techniques in microprocessor-based system design. Softw. Microsystems Parag K. Lala
1984	J	`jnl`	Redefinable crossassembler for horizontally microprogrammable processors. Microprocess. Microsystems Nigel F. Scholes, Gary Morgan, Parag K. Lala
1981	J	`jnl`	Testing using a minimal number of instructions. Microprocess. Microsystems Parag K. Lala