Paolo Meloni - RankMe

97 papers A 5B 1C 7Journal 42Unranked 42

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. IEEE Trans. Biomed. Circuits Syst. Paola Busia, Matteo Antonio Scrugli, Victor Jean-Baptiste Jung, Luca Benini, Paolo Meloni
2025	J	`jnl`	ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs. IEEE Trans. Circuits Syst. II Express Briefs Gianluca Leone, Paola Busia, Mauro Orrú, Luigi Raffo, Paolo Meloni
2025	A	`conf`	Enabling SNN-Based Near-MEA Neural Decoding with Channel Selection: An Open-HW Approach. DATE Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni
2025	—	`conf`	Endoscopy Image Classification for Wireless Capsules with CNNs on Microcontroller-Based Platforms. DASIP Paola Busia, Andrea Pinna, Paolo Meloni
2025	J	`jnl`	Real-Time sEMG Processing With Spiking Neural Networks on a Low-Power 5K-LUT FPGA. IEEE Trans. Biomed. Circuits Syst. Matteo Antonio Scrugli, Gianluca Leone, Paola Busia, Luigi Raffo, Paolo Meloni
2025	—	`conf`	SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference. CF (Companion) Luca Martis, Gianluca Leone, Luigi Raffo, Paolo Meloni
2025	J	`jnl`	SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Gianluca Leone, Matteo Antonio Scrugli, Lorenzo Badas, Luca Martis, Luigi Raffo, Paolo Meloni
2025	J	`jnl`	Wearable Epilepsy Seizure Detection on FPGA With Spiking Neural Networks. IEEE Trans. Biomed. Circuits Syst. Paola Busia, Gianluca Leone, Andrea Matticola, Luigi Raffo, Paolo Meloni
2024	J	`jnl`	A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. CoRR Paola Busia, Matteo Antonio Scrugli, Victor Jean-Baptiste Jung, Luca Benini, Paolo Meloni
2024	—	`conf`	Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry. UMAP (Adjunct Publication) Paola Busia, Claudio Marche, Paolo Meloni, Diego Reforgiato Recupero
2024	—	`conf`	Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. ARC Paolo Meloni, Paola Busia, Gianluca Leone, Luca Martis, Matteo Antonio Scrugli
2024	A	`conf`	On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis. DATE Matteo Antonio Scrugli, Paola Busia, Gianluca Leone, Paolo Meloni
2024	J	`jnl`	Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs. IEEE Trans. Biomed. Circuits Syst. Paola Busia, Andrea Cossettini, Thorir Mar Ingolfsson, Simone Benatti, Alessio Burrello, Victor J. B. Jung, Moritz Scherer, Matteo Antonio Scrugli, Adriano Bernini, Pauline Ducouret, Philippe Ryvlin, Paolo Meloni, Luca Benini
2024	—	`conf`	Spiking Neural Networks for Near-Sensor Processing: An Open-Hardware Experience. CPS Summer School, PhD Workshop Luca Martis, Gianluca Leone, Luigi Raffo, Paolo Meloni
2024	—	`conf`	sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA. DASIP Matteo Antonio Scrugli, Gianluca Leone, Paola Busia, Paolo Meloni
2023	J	`jnl`	A Microcontroller-Based Platform for Cognitive Tracking of Sensorimotor Training. IEEE Access Matteo Antonio Scrugli, Bojan Blazica, Luigi Raffo, Paolo Meloni
2023	J	`jnl`	An Automated Design Flow for Adaptive Neural Network Hardware Accelerators. J. Signal Process. Syst. Francesco Ratto, Ángela Porras Máinez, Carlo Sau, Paolo Meloni, Gianfranco Deriu, Stefano Delucchi, Massimo Massa, Luigi Raffo, Francesca Palumbo
2023	J	`jnl`	On-FPGA Spiking Neural Networks for End-to-End Neural Decoding. IEEE Access Gianluca Leone, Luigi Raffo, Paolo Meloni
2023	—	`conf`	On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. ARC Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni
2023	—	`conf`	Spiking Neural Networks for Integrated Reach-to-Grasp Decoding on FPGAs. BioCAS Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni
2022	J	`jnl`	A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA. IEEE Access Gianluca Leone, Luigi Raffo, Paolo Meloni
2022	—	`conf`	An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition. DASIP Matteo Antonio Scrugli, Bojan Blazica, Paolo Meloni
2022	J	`jnl`	An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things. IEEE Access Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
2022	J	`jnl`	An adaptable cognitive microcontroller node for fitness activity recognition. CoRR Matteo Antonio Scrugli, Bojan Blazica, Paolo Meloni
2022	—	`conf`	Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems. DASIP Paola Busia, Ilias Theodorakopoulos, Vasileios K. Pothos, Nikos Fragoulis, Paolo Meloni
2022	—	`conf`	EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices. BioCAS Paola Busia, Andrea Cossettini, Thorir Mar Ingolfsson, Simone Benatti, Alessio Burrello, Moritz Scherer, Matteo Antonio Scrugli, Paolo Meloni, Luca Benini
2022	C	`conf`	Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks. IECON Paolo Meloni, Alessandro Serpi
2022	J	`jnl`	Target-Aware Neural Architecture Search and Deployment for Keyword Spotting. IEEE Access Paola Busia, Gianfranco Deriu, Luca Rinelli, Cristina Chesta, Luigi Raffo, Paolo Meloni
2021	J	`jnl`	ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge. IEEE Access Paola Busia, Svetlana Minakova, Todor P. Stefanov, Luigi Raffo, Paolo Meloni
2021	J	`jnl`	An adaptive cognitive sensor node for ECG monitoring in the Internet of Medical Things. CoRR Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
2021	J	`jnl`	Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler
2021	—	`conf`	Task-Specific Automation in Deep Learning Processes. DEXA Workshops Georg Buchgeher, Gerald Czech, Adriano Souza Ribeiro, Werner Kloihofer, Paolo Meloni, Paola Busia, Gianfranco Deriu, Maura Pintor, Battista Biggio, Cristina Chesta, Luca Rinelli, David Solans, Manuel Portela
2020	C	`conf`	Biosensing IoT Platform for Water Management in Vineyards. ISCAS Silvia Loddo, M. Soccol, A. Perra, M. Ucchesu, Paolo Meloni, Massimo Barbaro, Mauro Lo Cascio, C. Sirca
2020	J	`jnl`	Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. IEEE Embed. Syst. Lett. Paolo Meloni, Daniela Loi, Gianfranco Deriu, Marco Carreras, Francesco Conti, Alessandro Capotondi, Davide Rossi
2020	J	`jnl`	Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. Marco Carreras, Gianfranco Deriu, Luigi Raffo, Luca Benini, Paolo Meloni
2020	J	`jnl`	Optimizing Temporal Convolutional Network inference on FPGA-based accelerators. CoRR Marco Carreras, Gianfranco Deriu, Luigi Raffo, Luca Benini, Paolo Meloni
2020	J	`jnl`	ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays. IEEE Access Gianluca Leone, Luigi Raffo, Paolo Meloni
2019	—	`conf`	A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties. NER Sara Zaher, Davide Lonardoni, Fabio Boi, Giovanni Pietro Seu, Gian Nicola Angotzi, Paolo Meloni, Luca Berdondini
2019	—	`conf`	A runtime-adaptive cognitive IoT node for healthcare monitoring. CF Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
2019	—	`conf`	CNN hardware acceleration on a low-power and low-cost APSoC. DASIP Paolo Meloni, Antonio Garufi, Gianfranco Deriu, Marco Carreras, Daniela Loi
2019	—	`conf`	Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0. CPS Summer School, PhD Workshop Marco Carreras, Gianfranco Deriu, Paolo Meloni
2019	—	`conf`	Optimization and deployment of CNNs at the edge: the ALOHA experience. CF Paolo Meloni, Daniela Loi, Paola Busia, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Todor P. Stefanov, Svetlana Minakova, Francesco Conti, Luca Benini, Maura Pintor, Battista Biggio, Bernhard Moser, Natalia Shepeleva, Nikos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
2019	—	`conf`	Runtime-Adaptive Cognitive IoT Nodes. CPS Summer School, PhD Workshop Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
2018	—	`conf`	ALOHA: an architectural-aware framework for deep learning at the edge. INTESA@ESWEEK Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Bernhard Moser, Natalia Shepeleva, Francesco Conti, Luca Benini, Oscar Ripolles, David Solans, Maura Pintor, Battista Biggio, Todor P. Stefanov, Svetlana Minakova, Nikolaos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
2018	—	`conf`	Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project. ICM Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Maura Pintor, Battista Biggio, Oscar Ripolles, David Solans, Francesco Conti, Luca Benini, Todor P. Stefanov, Svetlana Minakova, Bernhard Moser, Natalia Shepeleva, Michael Masin, Francesca Palumbo, Nikos Fragoulis, Ilias Theodorakopoulos
2018	J	`jnl`	Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays. IEEE Trans. Biomed. Circuits Syst. Giovanni Pietro Seu, Gian Nicola Angotzi, Fabio Boi, Luigi Raffo, Luca Berdondini, Paolo Meloni
2018	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. ACM Trans. Reconfigurable Technol. Syst. Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2017	J	`jnl`	Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing. IEEE Embed. Syst. Lett. Carlo Sau, Francesca Palumbo, Maxime Pelcat, Julien Heulot, Erwan Nogues, Daniel Ménard, Paolo Meloni, Luigi Raffo
2017	—	`conf`	Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture. IPDPS Workshops Francesca Palumbo, Carlo Sau, Danilo Pani, Paolo Meloni, Luigi Raffo
2017	J	`jnl`	NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. CoRR Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
2017	—	`conf`	On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration. IPDPS Workshops Giovanni Pietro Seu, Gian Nicola Angotzi, Giuseppe Tuveri, Luigi Raffo, Luca Berdondini, Alessandro Maccione, Paolo Meloni
2017	J	`jnl`	Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy. J. Signal Process. Syst. Francesca Palumbo, Tiziana Fanni, Carlo Sau, Paolo Meloni
2017	J	`jnl`	Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. J. Syst. Archit. Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo
2016	—	`conf`	A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. ReConFig Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016	J	`jnl`	Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
2016	—	`conf`	Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. Conf. Computing Frontiers Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
2016	—	`conf`	Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms. SiPS Francesca Palumbo, Carlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo
2016	—	`conf`	Demo: Reconfigurable Platform Composer Tool. DASIP Carlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo, Maxime Pelcat, Francesca Palumbo
2016	J	`jnl`	MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation. Microprocess. Microsystems Paolo Meloni, Francesca Palumbo, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo
2016	J	`jnl`	Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures. J. Electr. Comput. Eng. Francesca Palumbo, Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo
2016	J	`jnl`	On-the-fly adaptivity for process networks over shared-memory platforms. Microprocess. Microsystems Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti, Luigi Raffo
2016	—	`conf`	Power and clock gating modelling in coarse grained reconfigurable systems. Conf. Computing Frontiers Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo
2015	—	`conf`	Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. DASIP Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo
2015	—	`conf`	Power modelling for saving strategies in coarse grained reconfigurable systems. ReConFig Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo
2015	—	`conf`	Reconfigurable coprocessors synthesis in the MPEG-RVC domain. ReConFig Carlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo, Francesca Palumbo
2014	J	`jnl`	A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding. IEEE J. Emerg. Sel. Topics Circuits Syst. Nicola Carta, Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo
2014	—	`conf`	A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. MES Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014	—	`conf`	Online process transformation for polyhedral process networks in shared-memory MPSoCs. MECO Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
2014	J	`jnl`	The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. J. Real Time Image Process. Francesca Palumbo, Nicola Carta, Danilo Pani, Paolo Meloni, Luigi Raffo
2013	—	`conf`	A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs. PECCS Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Giuseppe Tuveri
2013	—	`conf`	A runtime adaptive H.264 video-decoding MPSoC platform. DASIP Giuseppe Tuveri, Simone Secchi, Paolo Meloni, Luigi Raffo, Emanuele Cannella
2013	J	`jnl`	A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project. Microprocess. Microsystems Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni, Todor P. Stefanov, Leandro Fiorin, Luigi Raffo, Mariagiovanna Sami
2013	J	`jnl`	ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, Giuseppe Notarangelo
2013	—	`conf`	Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy. DASIP Paolo Meloni, Christophe Jégo
2012	C	`conf`	ASAM: Automatic Architecture Synthesis and Application Mapping. DSD Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo
2012	J	`jnl`	Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. VLSI Design Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, Todor P. Stefanov
2012	—	`conf`	Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. ICSAMOS Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel
2012	J	`jnl`	Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. VLSI Design Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer
2012	A	`conf`	Exploiting binary translation for fast ASIP design space exploration on FPGAs. DATE Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer
2012	C	`conf`	System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach. DSD Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Emanuele Cannella, Todor P. Stefanov, Onur Derin, Leandro Fiorin, Mariagiovanna Sami
2012	J	`jnl`	Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs. Adv. Softw. Eng. Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Emanuele Cannella
2011	—	`conf`	Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not? ESTIMedia Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Meloni, Olaf Neugebauer, Andy D. Pimentel
2010	J	`jnl`	An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. IEEE Embed. Syst. Lett. Paolo Meloni, Simone Secchi, Luigi Raffo
2010	C	`conf`	Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC Paolo Meloni, Simone Secchi, Luigi Raffo
2010	B	`conf`	Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. ISPASS Simone Secchi, Paolo Meloni, Luigi Raffo
2007	J	`jnl`	A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini
2007	J	`jnl`	Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini
2007	—	`conf`	NoC Design and Implementation in 65nm Technology. NOCS Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
2007	C	`conf`	On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. DSD Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo
2007	J	`jnl`	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006	—	`conf`	Area and Power Modeling Methodologies for Networks-on-Chip. Nano-Net Paolo Meloni, Salvatore Carta, Roberto Argiolas, Luigi Raffo, Federico Angiolini
2006	A	`conf`	Contrasting a NoC and a traditional interconnect fabric with layout awareness. DATE Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
2006	C	`conf`	Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006	—	`conf`	Designing Routing and Message-Dependent Deadlock Free Networks on Chips. VLSI-SoC (Selected Papers) Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006	A	`conf`	Designing application-specific networks on chips with floorplan information. ICCAD Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006	—	`conf`	Routing Aware Switch Hardware Customization for Networks on Chips. Nano-Net Paolo Meloni, Srinivasan Murali, Salvatore Carta, Massimo Camplani, Luigi Raffo, Giovanni De Micheli
2005	—	`conf`	Networks on Chips: A Synthesis Perspective. PARCO Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo