Paolo Mantovani

38 papers A* 3A 5B 1Misc 2Journal 15Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	EPOCHS-1: A 12 nm Highly Heterogeneous Open-Source SoC With Distributed Coin-Based Power Management and Integrated Hybrid Voltage Regulation. IEEE J. Solid State Circuits Joseph Zuckerman, Martin Cochet, Maico Cassel dos Santos, Erik Jens Loscalzo, Karthik Swaminathan, Tianyu Jia, Davide Giri, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Samira Zaliasl, Michael Lekas, Stephen Cahill, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, Sarita V. Adve, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Pradip Bose, Luca P. Carloni
2024	—	`conf`	14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei
2024	B	`conf`	Mozart: Taming Taxes and Composing Accelerators with Shared-Memory. PACT Vignesh Suresh, Bakshree Mishra, Ying Jing, Zeran Zhu, Naiyin Jin, Charles Block, Paolo Mantovani, Davide Giri, Joseph Zuckerman, Luca P. Carloni, Sarita V. Adve
2023	J	`jnl`	SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. IEEE Des. Test Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P. Carloni
2022	—	`conf`	A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose
2022	A	`conf`	A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose
2022	J	`jnl`	Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. CoRR Joseph Zuckerman, Paolo Mantovani, Davide Giri, Luca P. Carloni
2021	J	`jnl`	Accelerator Integration for Open-Source SoC Design. IEEE Micro Davide Giri, Kuan-Lin Chiu, Guy Eichler, Paolo Mantovani, Luca P. Carloni
2021	A*	`conf`	Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. MICRO Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni
2021	J	`jnl`	Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. CoRR Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca P. Carloni
2020	A	`conf`	Agile SoC Development with Open ESP : Invited Paper. ICCAD Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
2020	J	`jnl`	Agile SoC Development with Open ESP. CoRR Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
2020	A	`conf`	ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. DATE Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni
2020	J	`jnl`	ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. CoRR Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni
2020	—	`conf`	HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis. CICC Paolo Mantovani, Robert Margelli, Davide Giri, Luca P. Carloni
2019	J	`jnl`	COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators. CoRR Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2019	—	`conf`	Runtime reconfigurable memory hierarchy in embedded scalable platforms. ASP-DAC Davide Giri, Paolo Mantovani, Luca P. Carloni
2019	—	`conf`	Teaching Heterogeneous Computing with System-Level Design Methods. WCAE@ISCA Luca P. Carloni, Emilio G. Cota, Giuseppe Di Guglielmo, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca Piccolboni, Michele Petracca
2019	A	`conf`	Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs. ISLPED Kshitij Bhardwaj, Paolo Mantovani, Luca P. Carloni, Steven M. Nowick
2018	J	`jnl`	Accelerators and Coherence: An SoC Perspective. IEEE Micro Davide Giri, Paolo Mantovani, Luca P. Carloni
2018	—	`conf`	NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. NOCS Davide Giri, Paolo Mantovani, Luca P. Carloni
2017	—	`conf`	Broadening the exploration of the accelerator design space in embedded scalable platforms. HPEC Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2017	J	`jnl`	COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators. ACM Trans. Embed. Comput. Syst. Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2017	—	`—`	Scalable System-on-Chip Design. Paolo Mantovani
2017	—	`conf`	System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip. NOCS Young-Jin Yoon, Paolo Mantovani, Luca P. Carloni
2017	J	`jnl`	System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2016	A*	`conf`	An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems. DAC Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Kenneth L. Shepard, Luca P. Carloni
2016	A	`conf`	Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration. ICS Emilio G. Cota, Paolo Mantovani, Luca P. Carloni
2016	Misc	`conf`	Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip. CASES Paolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, Luca P. Carloni
2016	—	`conf`	High-level synthesis of accelerators in embedded scalable platforms. ASP-DAC Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2016	—	`conf`	On the design of scalable and reusable accelerators for big data applications. Conf. Computing Frontiers Christian Pilato, Qirui Xu, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2015	J	`jnl`	A synchronous latency-insensitive RISC for better than worst-case design. Integr. Mario R. Casu, Paolo Mantovani
2015	A*	`conf`	An Analysis of Accelerator Coupling in Heterogeneous Architectures. DAC Emilio G. Cota, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2014	J	`jnl`	Accelerator Memory Reuse in the Dark Silicon Era. IEEE Comput. Archit. Lett. Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni
2014	Misc	`conf`	System-level memory optimization for high-level synthesis of component-based SoCs. CODES+ISSS Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
2012	J	`jnl`	A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI. IEEE J. Solid State Circuits Noah Sturcken, Michele Petracca, Steve B. Warren, Paolo Mantovani, Luca P. Carloni, Angel V. Peterchev, Kenneth L. Shepard
2011	—	`conf`	Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study. ACM Great Lakes Symposium on VLSI Mario R. Casu, Stefano Colazzo, Paolo Mantovani
1996	J	`jnl`	On maximal intermediate predicate constructive logics. Stud Logica Alessandro Avellone, Camillo Fiorentini, Paolo Mantovani, Pierangelo Miglioli