Paolo Madoglio

16 papers C 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET.
IEEE J. Solid State Circuits
Paolo Madoglio, Yorgos Palaskas, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Dimo Martev, Timo Gossmann, Andreas Holm, Zdravko Boos
2020 C conf
Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.
ISCAS
Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot
2019 — conf
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET.
ESSCIRC
Yorgos Palaskas, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Zdravko Boos, Paolo Madoglio, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer, Thomas Bauernfeind
2017 — conf
13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.
ISSCC
Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas
2013 J jnl
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.
IEEE J. Solid State Circuits
Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2012 J jnl
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.
IEEE J. Solid State Circuits
Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas
2012 — conf
A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.
ISSCC
Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas
2012 — conf
A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.
ISSCC
Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas
2012 — conf
A digital fractional-N PLL with a 3mW 0.004mm
ESSCIRC
Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2010 J jnl
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.
IEEE J. Solid State Circuits
Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas
2010 J jnl
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.
EURASIP J. Embed. Syst.
Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
2010 J jnl
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2009 — conf
A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving.
ESSCIRC
Paolo Madoglio, Ashoke Ravi, Luis Cuellar, Stefano Pellerano, Parmoon Seddighrad, Ismael Lomeli, Yorgos Palaskas
2009 J jnl
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS.
IEEE J. Solid State Circuits
Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas
2009 — conf
A 4.75GHz fractional frequency divider with digital spur calibration in 45nm CMOS.
ISSCC
Stefano Pellerano, Paolo Madoglio, Yorgos Palaskas
2007 J jnl
Quantization Effects in All-Digital Phase-Locked Loops.
IEEE Trans. Circuits Syst. II Express Briefs
Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita