Paolo Ienne - RankMe

245 papers A* 14A 63B 25C 6Misc 22Journal 58Unranked 53

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators. FPGA Canberk Sönmez, Mohamed Shahawy, Paolo Ienne
2026	—	`conf`	Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. ASPLOS (2) Yann Herklotz, Ayatallah Elakhras, Martina Camaioni, Paolo Ienne, Lana Josipovic, Thomas Bourgeat
2026	A	`conf`	Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. FPGA Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne
2025	J	`jnl`	Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration. CoRR Mohamed Shahawy, Julien de Castelnau, Paolo Ienne
2025	B	`conf`	Compile in Seconds and Run on an FPGA with DynaRapid. FPL Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2025	Misc	`conf`	DRSA: Accelerating Macro Placement on Commercial FPGAs. FCCM Menzo Bouaissi, Paolo Ienne, Lana Josipovic, Andrea Guerrieri
2025	—	`conf`	ElasticMiter: Formally Verified Dataflow Circuit Rewrites. ASPLOS (2) Ayatallah Elakhras, Jiahui Xu, Martin Erhart, Paolo Ienne, Lana Josipovic
2025	A	`conf`	FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs. ICCAD Louis Coulon, Adham Ragab, Jason Anderson, Mirjana Stojilovic, Paolo Ienne
2025	A	`conf`	FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. FPGA Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne
2025	Misc	`conf`	HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance. FCCM Canberk Sönmez, Mohamed Shahawy, Paolo Ienne
2025	—	`conf`	The Rise and Fall of Automatic Instruction-Set Extensions. ASAP Paolo Ienne, Laura Pozzi, Philip Brisk
2024	J	`jnl`	Could ChatGPT get an Engineering Degree? Evaluating Higher Education Vulnerability to AI Assistants. CoRR Beatriz Borges, Negar Foroutan, Deniz Bayazit, Anna Sotnikova, Syrielle Montariol, Tanya Nazaretzky, Mohammadreza Banaei, Alireza Sakhaeirad, Philippe Servant, Seyed Parsa Neshaei, Jibril Frej, Angelika Romanou, Gail Weiss, Sepideh Mamooler, Zeming Chen, Simin Fan, Silin Gao, Mete Ismayilzada, Debjit Paul, Alexandre Schöpfer, Andrej Janchevski, Anja Tiede, Clarence Linden, Emanuele Troiani, Francesco Salvi, Freya Behrens, Giacomo Orsi, Giovanni Piccioli, Hadrien Sevel, Louis Coulon, Manuela Pineros-Rodriguez, Marin Bonnassies, Pierre Hellich, Puck van Gerwen, Sankalp Gambhir, Solal Pirelli, Thomas Blanchard, Timothée Callens, Toni Abi Aoun, Yannick Calvino Alonso, Yuri Cho, Alberto Silvio Chiappa, Antonio Sclocchi, Étienne Bruno, Florian Hofhammer, Gabriel Pescia, Geovani Rizk, Leello Dadi, Lucas Stoffl, Manoel Horta Ribeiro, Matthieu Bovel, Yueyang Pan, Aleksandra Radenovic, Alexandre Alahi, Alexander Mathis, Anne-Florence Bitbol, Boi Faltings, Cécile Hébert, Devis Tuia, François Maréchal, George Candea, Giuseppe Carleo, Jean-Cédric Chappelier, Nicolas Flammarion, Jean-Marie Fürbringer, Jean-Philippe Pellet, Karl Aberer, Lenka Zdeborová, Marcel Salathé, Martin Jaggi, Martin Rajman, Mathias Payer, Matthieu Wyart, Michael Gastpar, Michele Ceriotti, Ola Svensson, Olivier Lévêque, Paolo Ienne, Rachid Guerraoui, Robert West, Sanidhya Kashyap, Valerio Piazza, Viesturs Simanis, Viktor Kuncak, Volkan Cevher, Philippe Schwaller, Sacha Friedli, Patrick Jermann, Tanja Käser, Antoine Bosselut
2024	B	`conf`	DynaRapid: Fast-Tracking from C to Routed Circuits. FPL Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2024	A	`conf`	DynaRapid: From C to FPGA in a Few Seconds. FPGA Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne
2024	J	`jnl`	Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. ACM Trans. Reconfigurable Technol. Syst. Stefan Nikolic, Paolo Ienne
2024	B	`conf`	FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs. FPL Canberk Sönmez, Mohamed Shahawy, Cemalettin Cem Belentepe, Paolo Ienne
2024	Misc	`conf`	HardCilk: Cilk-like Task Parallelism for FPGAs. FCCM Mohamed Shahawy, Canberk Sönmez, Cemalettin Belentepe, Paolo Ienne
2024	A	`conf`	Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. FPGA Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2023	J	`jnl`	Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR Jovan Blanusa, Kubilay Atasu, Paolo Ienne
2023	J	`jnl`	Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. Jovan Blanusa, Kubilay Atasu, Paolo Ienne
2023	J	`jnl`	Introduction to the Special Section on FPGA 2022. ACM Trans. Reconfigurable Technol. Syst. Paolo Ienne
2023	A	`ed.`	Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023 FPGA Paolo Ienne, Zhiru Zhang
2023	A	`conf`	Regularity Matters: Designing Practical FPGA Switch-Blocks. FPGA Stefan Nikolic, Paolo Ienne
2023	J	`jnl`	Resource Sharing in Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2023	A	`conf`	Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. FPGA Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2022	B	`conf`	A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. FPL Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic
2022	J	`jnl`	Buffer Placement and Sizing for High-Performance Dataflow Circuits. ACM Trans. Reconfigurable Technol. Syst. Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
2022	J	`jnl`	DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2022	J	`jnl`	Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. Stefan Nikolic, Grace Zgheib, Paolo Ienne
2022	A	`ed.`	FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022 FPGA Michael Adler, Paolo Ienne
2022	J	`jnl`	From C/C++ Code to High-Performance Dataflow Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2022	J	`jnl`	Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Mikhail Asiatici, Paolo Ienne
2022	Misc	`conf`	Resource Sharing in Dataflow Circuits. FCCM Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2022	B	`conf`	Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA Jovan Blanusa, Paolo Ienne, Kubilay Atasu
2022	J	`jnl`	Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR Jovan Blanusa, Paolo Ienne, Kubilay Atasu
2022	B	`conf`	Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. FPL Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne
2021	A	`conf`	Global Is the New Local: FPGA Architecture at 5nm and Beyond. FPGA Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne
2021	J	`jnl`	How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. J. Signal Process. Syst. Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2021	A*	`conf`	Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. ISCA Mikhail Asiatici, Paolo Ienne
2021	A	`conf`	Resource Sharing in Dataflow Circuits. FPGA Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne
2021	B	`conf`	Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. FPL Stefan Nikolic, Paolo Ienne
2020	A	`conf`	Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella
2020	A	`conf`	Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson
2020	—	`conf`	FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. ASAP Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2020	A	`conf`	Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. FPGA Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2020	J	`jnl`	Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
2020	—	`conf`	Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu
2020	A	`conf`	Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA Stefan Nikolic, Grace Zgheib, Paolo Ienne
2020	B	`conf`	Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL Stefan Nikolic, Grace Zgheib, Paolo Ienne
2019	B	`conf`	DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. FPL Mikhail Asiatici, Paolo Ienne
2019	B	`conf`	Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL Stefan Nikolic, Grace Zgheib, Paolo Ienne
2019	—	`conf`	In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. FPT Gabor Csordas, Mikhail Asiatici, Paolo Ienne
2019	A	`conf`	On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. FPGA Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne
2019	—	`conf`	Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. FPT Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne
2019	J	`jnl`	Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. IEEE Access Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne
2019	A	`conf`	Speculative Dataflow Circuits. FPGA Lana Josipovic, Andrea Guerrieri, Paolo Ienne
2019	A	`conf`	Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. FPGA Mikhail Asiatici, Paolo Ienne
2018	—	`conf`	A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. AHS Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
2018	A	`conf`	Dynamically Scheduled High-level Synthesis. FPGA Lana Josipovic, Radhika Ghosal, Paolo Ienne
2018	C	`conf`	Exploiting Compute Caches for Memory Bound Vector Operations. SBAC-PAD João Vieira, Nuno Roma, Pedro Tomás, Paolo Ienne, Gabriel Falcão Paiva Fernandes
2018	A	`conf`	FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS FPGA Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2018	A	`conf`	LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). FPGA Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
2018	—	`ch.`	Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne
2017	J	`jnl`	An Accelerator for High Efficient Vision Processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam
2017	Misc	`conf`	An Out-of-Order Load-Store Queue for Spatial Computing. FCCM Lana Josipovic, Philip Brisk, Paolo Ienne
2017	J	`jnl`	An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. Lana Josipovic, Philip Brisk, Paolo Ienne
2017	A*	`conf`	Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne
2017	J	`jnl`	Design Space Exploration of LDPC Decoders Using High-Level Synthesis. IEEE Access João Andrade, Nithin George, Kimon Karras, David Novo, Frederico Pratas, Leonel Sousa, Paolo Ienne, Gabriel Falcão, Vítor Silva
2017	B	`conf`	Evaluating FPGA clusters under wide ranges of design parameters. FPL Grace Zgheib, Paolo Ienne
2017	Misc	`conf`	From C to elastic circuits. ACSSC Lana Josipovic, Philip Brisk, Paolo Ienne
2017	—	`conf`	Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	A	`conf`	NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang
2017	J	`jnl`	Virtualized Execution Runtime for FPGA Accelerators in the Cloud. IEEE Access Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
2016	B	`ed.`	26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	—	`conf`	Automatic wire modeling to explore novel FPGA architectures. FPT Grace Zgheib, Paolo Ienne
2016	J	`jnl`	Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE Trans. Very Large Scale Integr. Syst. Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi
2016	B	`conf`	Designing a virtual runtime for FPGA accelerators in the cloud. FPL Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
2016	—	`conf`	Enriching C-based High-Level Synthesis with parallel pattern templates. FPT Lana Josipovic, Nithin George, Paolo Ienne
2016	A	`conf`	FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne
2016	A	`conf`	Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
2016	B	`conf`	Fast hierarchical NPN classification. FPL Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
2016	J	`jnl`	Guest Editorial: Special Issue on Models and Methodologies for System Design. ACM Trans. Embed. Comput. Syst. Paolo Ienne, Jean-Pierre Talpin
2016	J	`jnl`	Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE Trans. Computers Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
2016	A	`conf`	Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
2016	A	`conf`	Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. ICCAD Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner
2016	A	`conf`	Instruction Set Extensions for secure applications. DATE Francesco Regazzoni, Paolo Ienne
2016	J	`jnl`	Introduction: Special Section on Architecture of Future Many Core Systems. Microprocess. Microsystems Hossein Asadi, Paolo Ienne, Hamid Sarbazi-Azad
2016	B	`conf`	Preface. FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2015	B	`conf`	A technology mapper for depth-constrained FPGA logic cells. FPL Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
2015	—	`ed.`	Advanced Parallel Processing Technologies - 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings APPT Yunji Chen, Paolo Ienne, Qing Ji
2015	J	`jnl`	Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne
2015	B	`conf`	Automatic support for multi-module parallelism from computational patterns. FPL Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne
2015	J	`jnl`	Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2015	—	`conf`	Exploring Automatically Generated Platforms in High Performance FPGAs. PARCO Panagiotis Skrimponis, Georgios Zindros, Ioannis Parnassos, Muhsen Owaida, Nikolaos Bellas, Paolo Ienne
2015	Misc	`conf`	Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. FCCM João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
2015	B	`conf`	From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. FPL João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes
2015	—	`conf`	FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne
2015	—	`conf`	Improved carry chain mapping for the VTR flow. FPT Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
2015	J	`jnl`	Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. ACM Trans. Embed. Comput. Syst. Xavier Jimenez, David Novo, Paolo Ienne
2015	A	`conf`	Retraining-based timing error mitigation for hardware neural networks. DATE Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu
2015	A*	`conf`	ShiDianNao: shifting vision processing closer to the sensor. ISCA Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam
2014	Misc	`conf`	A low-cost memory interface for high-throughput accelerators. CASES Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu
2014	A	`conf`	Constrained interpolation for guided logic synthesis. ICCAD Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne
2014	A	`conf`	Energy efficient MIMO processing: A case study of opportunistic run-time approximations. DATE David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor
2014	B	`conf`	Hardware system synthesis from Domain-Specific Languages. FPL Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne
2014	J	`jnl`	Reconfigurable Computing. IEEE Micro Walid A. Najjar, Paolo Ienne
2014	A	`conf`	Revisiting and-inverter cones. FPGA Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
2014	A	`conf`	SKETCHILOG: Sketching combinational circuits. DATE Andrew Becker, David Novo, Paolo Ienne
2014	J	`jnl`	Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
2014	J	`jnl`	Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2014	A	`conf`	Wear unleveling: improving NAND flash lifetime by balancing page endurance. FAST Xavier Jimenez, David Novo, Paolo Ienne
2013	Misc	`conf`	A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM Madhura Purnaprajna, Paolo Ienne
2013	A	`conf`	Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. DATE David Novo, Sara El Alaoui, Paolo Ienne
2013	A	`conf`	An EDA-friendly protection scheme against side-channel attacks. DATE Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne
2013	Misc	`conf`	Automated circuit elaboration from incomplete architectural descriptions. ACSSC Andrew Becker, David Novo, Paolo Ienne
2013	—	`conf`	Cracking the complexity of fixed-point refinement in complex wireless systems. SiPS David Novo, I. Tzimi, Ubaid Ahmad, Paolo Ienne, Francky Catthoor
2013	A	`conf`	Elastic CGRAs. FPGA Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu
2013	A	`conf`	Fast and accurate BER estimation methodology for I/O links based on extreme value theory. DATE Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis
2013	—	`conf`	Making domain-specific hardware synthesis tools cost-efficient. FPT Nithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne
2013	A	`conf`	Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. DATE Xavier Jimenez, David Novo, Paolo Ienne
2013	J	`jnl`	Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
2013	A	`conf`	Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013	B	`conf`	Shadow And-Inverter Cones. FPL Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
2013	A	`conf`	Sleuth: Automated Verification of Software Power Analysis Countermeasures. CHES Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne
2013	—	`conf`	Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement. NAS Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo Ienne
2012	J	`jnl`	An architecture-independent instruction shuffler to protect against side-channel attacks. ACM Trans. Archit. Code Optim. Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne P. Burleson
2012	—	`conf`	CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores. Euro-Par Shuai Jiao, Paolo Ienne, Xiaochun Ye, Da Wang, Dongrui Fan, Ninghui Sun
2012	—	`conf`	Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2012	J	`jnl`	Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Elisardo Antelo, David Hough, Paolo Ienne
2012	—	`ch.`	Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks. Fault Analysis in Cryptography Francesco Regazzoni, Luca Breveglieri, Paolo Ienne, Israel Koren
2012	J	`jnl`	Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. Madhura Purnaprajna, Paolo Ienne
2012	A	`conf`	Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
2012	A	`conf`	Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. FPGA Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne
2012	A	`conf`	Selective flexibility: Breaking the rigidity of datapath merging. DATE Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
2012	Misc	`conf`	Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
2012	A*	`conf`	Software controlled cell bit-density to improve NAND flash lifetime. DAC Xavier Jimenez, David Novo, Paolo Ienne
2011	C	`ed.`	20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011 IEEE Symposium on Computer Arithmetic Elisardo Antelo, David Hough, Paolo Ienne
2011	—	`ed.`	22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 ASAP Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca
2011	A*	`conf`	A first step towards automatic application of power analysis countermeasures. DAC Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne
2011	J	`jnl`	Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne
2011	B	`conf`	Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. FPL Hadi Parandeh-Afshar, Paolo Ienne
2011	A*	`conf`	Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. DAC Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici
2011	A	`conf`	Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne
2010	—	`conf`	A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul
2010	J	`jnl`	An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2010	J	`jnl`	Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010	A	`conf`	High performance comparison-based sorting algorithm on many-core GPUs. IPDPS Xiaochun Ye, Dongrui Fan, Wei Lin, Nan Yuan, Paolo Ienne
2010	Misc	`conf`	Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. FCCM Hadi Parandeh-Afshar, Paolo Ienne
2010	J	`jnl`	Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010	B	`conf`	Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2010	—	`conf`	Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
2009	A	`conf`	3D configuration caching for 2D FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
2009	A	`conf`	A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	A flexible DSP block to enhance FPGA arithmetic performance. FPT Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	—	`conf`	Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne
2009	—	`conf`	Arithmetic optimization for custom instruction set synthesis. SASP Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne
2009	C	`conf`	Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	J	`jnl`	Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2009	B	`conf`	Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009	Misc	`conf`	FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne
2009	J	`jnl`	Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	—	`conf`	From gates to multi-processors learning systems hands-on with FPGA4U in a computer science programme. WESE@ESWEEK Claudio Favi, René Beuchat, Xavier Jimenez, Paolo Ienne
2009	—	`conf`	Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	—	`conf`	Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne
2009	A	`conf`	Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009	—	`conf`	MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
2009	A	`conf`	Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	J	`jnl`	Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2009	B	`conf`	Using 3D integration technology to realize multi-context FPGAs. FPL Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009	A*	`conf`	Way Stealing: cache-assisted automatic instruction set extensions. DAC Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
2008	A	`conf`	A novel FPGA logic block for improved arithmetic performance. FPGA Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	A	`conf`	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	—	`conf`	Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. DFT Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren
2008	J	`jnl`	Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008	Misc	`conf`	Design space exploration for field programmable compressor trees. CASES Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008	—	`conf`	Efficient synthesis of compressor trees on FPGAs. ASP-DAC Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	—	`conf`	Error Protected Data Bus Inversion Using Standard DRAM Components. ISQED Maurizio Skerlj, Paolo Ienne
2008	—	`conf`	Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008	J	`jnl`	Guest Editorial Special Section on Application Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. Paolo Ienne, Peter Petrov
2008	A	`conf`	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008	Misc	`conf`	Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
2008	A	`conf`	Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007	—	`conf`	A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
2007	Misc	`conf`	An optimistic and conservative register assignment heuristic for chordal graphs. CASES Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007	A	`conf`	Automatic synthesis of compressor trees: reevaluating large counters. DATE Ajay Kumar Verma, Paolo Ienne
2007	A*	`conf`	Enhancing FPGA Performance for Arithmetic Circuits. DAC Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar
2007	J	`jnl`	ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007	—	`conf`	Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC Ajay Kumar Verma, Paolo Ienne
2007	J	`jnl`	Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2007	A	`conf`	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007	—	`conf`	Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. ISQED Frederic Worm, Patrick Thiran, Paolo Ienne
2007	—	`conf`	Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. DFT Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar
2007	A*	`conf`	Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007	Misc	`conf`	Rethinking custom ISE identification: a new processor-agnostic method. CASES Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2006	C	`conf`	A Predictable Communication Scheme for Embedded Multiprocessor Systems. VLSI-SoC Mehmet Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
2006	A	`conf`	Automatic identification of application-specific functional units with architecturally visible storage. DATE Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006	A	`conf`	Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma
2006	C	`conf`	Designing Robust Checkers in the Presence of Massive Timing Errors. IOLTS Frederic Worm, Patrick Thiran, Paolo Ienne
2006	J	`jnl`	Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Laura Pozzi, Kubilay Atasu, Paolo Ienne
2006	J	`jnl`	ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Very Large Scale Integr. Syst. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2006	—	`conf`	Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. FPT Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele
2006	Misc	`conf`	Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
2006	A*	`conf`	Towards the automatic exploration of arithmetic-circuit architectures. DAC Ajay Kumar Verma, Paolo Ienne
2006	J	`jnl`	Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. Very Large Scale Integr. Syst. Miljan Vuletic, Laura Pozzi, Paolo Ienne
2005	—	`conf`	A Unified Coding Framework for Delay-Insensitivity. ASYNC Frederic Worm, Patrick Thiran, Paolo Ienne
2005	J	`jnl`	A robust self-calibrating transmission scheme for on-chip networks. IEEE Trans. Very Large Scale Integr. Syst. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
2005	—	`conf`	Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. ESTIMedia Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici
2005	Misc	`conf`	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne
2005	Misc	`conf`	Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES Laura Pozzi, Paolo Ienne
2005	A	`conf`	ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
2005	—	`conf`	Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. ISCAS (2) Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
2005	J	`jnl`	Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Des. Test Comput. Miljan Vuletic, Laura Pozzi, Paolo Ienne
2005	—	`conf`	Self-calibrating networks-on-chip. ISCAS (3) Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
2004	—	`conf`	Adding Limited Reconfigurability to Superscalar Processors. IEEE PACT Marc Epalza, Paolo Ienne, Daniel Mlynek
2004	—	`conf`	Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA Paolo Ienne, Ajay Kumar Verma
2004	C	`conf`	Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
2004	B	`conf`	Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004	—	`conf`	Dynamic Reallocation of Functional Units in Superscalar Processors. Asia-Pacific Computer Systems Architecture Conference Marc Epalza, Paolo Ienne, Daniel Mlynek
2004	A	`conf`	Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD Ajay Kumar Verma, Paolo Ienne
2004	A*	`conf`	Introduction of local memory elements in instruction set extensions. DAC Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
2004	J	`jnl`	On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. IEEE Des. Test Comput. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
2004	A	`conf`	Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
2004	—	`conf`	Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004	—	`conf`	Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. SoC Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
2004	A	`conf`	Soft self-synchronising codes for self-calibrating communication. ICCAD Frederic Worm, Paolo Ienne, Patrick Thiran
2004	Misc	`conf`	Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM Miljan Vuletic, Laura Pozzi, Paolo Ienne
2004	A*	`conf`	Virtual memory window for application-specific reconfigurable coprocessors. DAC Miljan Vuletic, Laura Pozzi, Paolo Ienne
2003	J	`jnl`	Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. Kubilay Atasu, Laura Pozzi, Paolo Ienne
2003	—	`conf`	Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
2003	A*	`conf`	Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC Kubilay Atasu, Laura Pozzi, Paolo Ienne
2002	—	`conf`	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
2002	—	`conf`	An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm
2002	A	`conf`	Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE Laura Pozzi, Miljan Vuletic, Paolo Ienne
1998	A*	`conf`	Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? DAC Paolo Ienne, Alexander Grießing
1997	Misc	`conf`	Digital Connectionist Hardware: Current Problems and Future Challenges. IWANN Paolo Ienne
1997	J	`jnl`	Modified self-organizing feature map algorithms for efficient digital hardware implementation. IEEE Trans. Neural Networks Paolo Ienne, Patrick Thiran, Nikolaos Vassilas
1996	J	`jnl`	Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator. Sci. Program. Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, Marc A. Viredaz
1996	—	`conf`	On modifications of Kohonen's feature map algorithm for an efficient parallel implementation. ICNN Nikolaos Vassilas, Patrick Thiran, Paolo Ienne
1996	J	`jnl`	Special-purpose digital hardware for neural networks: An architectural survey. J. VLSI Signal Process. Paolo Ienne, Thierry Cornu, Gary Kuhn
1995	J	`jnl`	GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. J. VLSI Signal Process. Paolo Ienne, Marc A. Viredaz
1995	—	`conf`	Horizontal Microcode Compaction for Programmable Systolic Accelerators. ASAP Paolo Ienne
1994	J	`jnl`	Bit-Serial Multipliers and Squarers. IEEE Trans. Computers Paolo Ienne, Marc A. Viredaz
1993	—	`conf`	GENES IV: A bit-serial processing element for a built-model neural-network accelerator. ASAP Paolo Ienne, Marc A. Viredaz
1993	—	`conf`	Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. ISER Francesco Mondada, Edoardo Franzi, Paolo Ienne