Pao-Lung Chen

18 papers C 1Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Fully Synthesizable Ultra- ${N}$ Audio Frequency Multiplier for HDMI Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Pao-Lung Chen
2019 — conf
An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering.
ISPACS
Pao-Lung Chen
2017 J jnl
A Reconfigurable TAF-DPS Frequency Synthesizer on FPGA Achieving 2 ppb Frequency Granularity and Two-Cycle Switching Speed.
IEEE Trans. Ind. Electron.
Liming Xiu, Pao-Lung Chen
2016 — conf
A low-cost carry look-ahead adder for flying-adder frequency synthesizer.
ICCE-TW
Pao-Lung Chen
2016 — conf
An open-loop fractional divider based on direct phase synthesis.
ICCE-TW
Pao-Lung Chen
2015 — conf
Carry randomization with fractional control of a De Bruijn sequence.
ICCE-TW
Pao-Lung Chen
2015 — conf
Digitally controlled oscillator with storage based randomization for spurs reduction.
ICCE-TW
Pao-Lung Chen, Ting-Yao Chen
2015 J jnl
Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method.
IEICE Trans. Electron.
Pao-Lung Chen, Da-Chen Lee, Wei-Chia Li
2013 — conf
A jumping algorithm for calibration in multiphase delay locked loop.
ICCA
Pao-Lung Chen
2011 J jnl
An Interpolated Flying-Adder-Based Frequency Synthesizer.
J. Electr. Comput. Eng.
Pao-Lung Chen, Chun-Chien Tsai
2011 — conf
Simulation-Based Analysis and Experimental Verification of Chaotic Circuits.
FIRA
Pao-Lung Chen, Ke-Xin Lin
2010 — conf
A multiphase all-digital delay-locked loop with reuse SAR.
APCCAS
Pao-Lung Chen, Tzu-Siang Wang, Jyun-Han Ciou
2010 J jnl
Subtraction Inversion for Delta Path's Hardware Simplification in MASH Delta-Sigma Modulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pao-Lung Chen
2008 C conf
Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop.
ISCAS
Pao-Lung Chen
2006 J jnl
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications.
IEEE J. Solid State Circuits
Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee
2005 J jnl
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Pao-Lung Chen, Chen-Yi Lee
2005 J jnl
A portable digitally controlled oscillator using novel varactors.
IEEE Trans. Circuits Syst. II Express Briefs
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee
2005 — conf
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.
ISCAS (5)
Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee