Panu Sjövall

12 papers B 1C 6Journal 1Unranked 3
YearRankTypeTitle / Venue / Authors
2025 C conf
High-Level Synthesis FPGA Implementation of Fractional Motion Estimation for HEVC and VVC.
VCIP
Jesse Smedberg, Panu Sjövall, Guillaume Gautier, Alexandre Mercat, Jarno Vanne
2025 C conf
ShapeFuture - Technical Progress After Year 1.
DSD
Norbert Druml, Martin Gschwandtner, Mayeul Jeannin, Rainer Matischek, Edgars Lielamurs, Maksis Celitans, Kaspars Ozols, Nurullah Demiralay, Besir Tayfur, Ismail Sinan Gulbas, Nadir Kucuk, Isa Kiyat, Yahya Nasolo, Jens Brandt, Noah Christoph Pütz, Thomas Bartz-Beielstein, Jose Isola, Nikola Mandic, Francesca Flamigni, Alexander Kuehhas, Gianluca Brilli, Paolo Burgio, Giacomo Paolieri, Jorge Villagra, Álvaro Flores Cueto, José Antonio Sánchez, Jacopo Sini, Massimo Violante, Lorenzo Giraudi, Paolo Santero, Uwe Kölbel, Moritz Schaffenroth, Panu Sjövall, Jarno Vanne, Morten Larsen, Nergis Gizem Yilmaz, Ziya Uygar Yengin, George Dimitrakopoulos
2025 — conf
uvgKvazaarHW: Open-Source Hardware HEVC Intra Encoder.
CF (Companion)
Panu Sjövall, Guillaume Gautier, Alexandre Mercat, Jarno Vanne
2023 B conf
FPGA-Accelerated HEVC Encoder for Energy-Efficient Multi-Access Edge Computing.
ICIP
Panu Sjövall, Alexandre Mercat, Jarno Vanne
2023 — —
Feasibility Study of High-Level Synthesis: Implementation of a Real-Time HEVC Intra Encoder on FPGA.
Panu Sjövall
2022 J jnl
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications.
ACM Trans. Design Autom. Electr. Syst.
Panu Sjövall, Ari Lemmetti, Jarno Vanne, Sakari Lahti, Timo D. Hämäläinen
2021 C conf
High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding.
ISCAS
Tero Partanen, Ari Lemmetti, Panu Sjövall, Jarno Vanne
2021 — conf
High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGA.
NorCAS
Panu Sjövall, Matti Rasinen, Ari Lemmetti, Jarno Vanne
2019 — conf
Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud.
NORCAS
Panu Sjövall, Arto Oinonen, Mikko Teuho, Jarno Vanne, Timo D. Hämäläinen
2019 C conf
Visualization of Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud.
VCIP
Panu Sjövall, Mikko Teuho, Arto Oinonen, Jarno Vanne, Timo D. Hämäläinen
2018 C conf
FPGA-Powered 4K120p HEVC Intra Encoder.
ISCAS
Panu Sjövall, Vili Viitamäki, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala
2018 C conf
Live Demonstration: 4K100p HEVC Intra Encoder.
ISCAS
Vili Viitamäki, Panu Sjövall, Jarno Vanne, Timo D. Hämäläinen, Ari Kulmala