Pallav Gupta

23 papers A* 1A 8C 1Misc 1Journal 11Unranked 1
YearRankTypeTitle / Venue / Authors
2025 J jnl
Empowering healthcare with BIEH - blockchain inter-operable electronic health record scheme.
Clust. Comput.
Pallav Gupta, Swarab Raul, S. Shoba, Karthika Veeramani
2018 A conf
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug.
ITC
Pallav Gupta
2018 A conf
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.
ITC
I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram
2015 J jnl
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. Very Large Scale Integr. Syst.
Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
2013 J jnl
NBTI-aware circuit node criticality computation.
ACM J. Emerg. Technol. Comput. Syst.
Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao
2012 J jnl
A physical design tool for carbon nanotube field-effect transistor circuits.
ACM J. Emerg. Technol. Comput. Syst.
Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang, Steven M. Rubin, Gilda Garretón, Jin He
2012 J jnl
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.
ACM Trans. Embed. Comput. Syst.
Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie
2012 A conf
Test generation for clock-domain crossing faults in integrated circuits.
DATE
Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
2011 A conf
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.
DATE
Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
2011 J jnl
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs.
ACM Trans. Design Autom. Electr. Syst.
Xiaofang (Maggie) Wang, Pallav Gupta
2011 — conf
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.
Asian Test Symposium
Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
2008 J jnl
Automatic Test Generation for Combinational Threshold Logic Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Pallav Gupta, Rui Zhang, Niraj K. Jha
2007 J jnl
A Test Generation Framework for Quantum Cellular Automata Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
2007 J jnl
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Zhang, Pallav Gupta, Niraj K. Jha
2006 J jnl
An Algorithm for Synthesis of Reversible Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
2006 A conf
Test generation for combinational quantum cellular automata (QCA) circuits.
DATE
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
2005 A* conf
Efficient fingerprint-based user authentication for embedded systems.
DAC
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005 Misc conf
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.
VLSI Design
Rui Zhang, Pallav Gupta, Niraj K. Jha
2005 J jnl
Threshold network synthesis and optimization and its application to nanotechnologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
2004 A conf
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.
DATE
Pallav Gupta, Niraj K. Jha
2004 C conf
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
ICCD
Pallav Gupta, Rui Zhang, Niraj K. Jha
2004 A conf
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.
DATE
Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
2003 A conf
A High-level Interconnect Power Model for Design Space Exploration.
ICCAD
Pallav Gupta, Lin Zhong, Niraj K. Jha