Pallabi Sarkar

15 papers Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2023 — conf
System Complexity Reduction Using 3-D Matrices and Novel Logic Gates.
ICCCNT
Nameshwari Verma, Pallabi Sarkar
2020 — conf
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography.
ICCE-Berlin
Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta
2019 J jnl
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag.
Pallabi Sarkar, Dipanjan Roy, Anirban Sengupta, Mrinal Kanti Naskar
2018 — conf
Obfuscation of Fault Secured DSP Design Through Hybrid Transformation.
ISVLSI
Anirban Sengupta, Shubha Neema, Pallabi Sarkar, Sri Harsha P, Saraju P. Mohanty, Mrinal Kanti Naskar
2018 J jnl
Optimizing DSP Cores Using Design Transformation [Hardware Matters].
IEEE Consumer Electron. Mag.
Dipanjan Roy, Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
2017 — conf
A Firefly Algorithm Driven Approach for High Level Synthesis.
iNIS
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
2017 J jnl
Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag.
Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, Mrinal Kanti Naskar
2015 — conf
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.
CCECE
Pallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar
2013 — conf
A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design.
ICACCI
Tulasi Krishna, Priyam Sachdeva, Suraj Kumar Dhanuka, Mohit Gagrani, Pallabi Sarkar
2012 J jnl
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm Evol. Comput.
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2012 J jnl
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocess. Microsystems
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
ACAI
Pallabi Sarkar, Reza Sedaghat, Anirban Sengupta
2011 — conf
Integrated design space exploration based on power-performance trade-off using genetic algorithm.
ACAI
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
2011 — conf
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal
2011 — conf
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
CCECE
Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal