Palkesh Jain

20 papers A* 1A 2Misc 2Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks.
ACM Trans. Design Autom. Electr. Syst.
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2021 J jnl
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks.
CoRR
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2021 — conf
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks.
ASP-DAC
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2020 J jnl
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks.
CoRR
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
2019 A conf
NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations.
ICCAD
Shashank Varshney, Hameedah Sultan, Palkesh Jain, Smruti R. Sarangi
2017 — —
Algorithms and methodologies for interconnect reliability analysis of integrated circuits.
Palkesh Jain
2017 J jnl
Fast Stochastic Analysis of Electromigration in Power Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Palkesh Jain, Vivek Mishra, Sachin S. Sapatnekar
2017 A* conf
Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays.
DAC
Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar
2016 J jnl
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects.
IEEE Trans. Very Large Scale Integr. Syst.
Palkesh Jain, Jordi Cortadella, Sachin S. Sapatnekar
2016 J jnl
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015 — conf
A retargetable and accurate methodology for logic-IP-internal electromigration assessment.
ASP-DAC
Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
2015 — conf
Impact on performance, power, area and wirelength using electromigration-aware cells.
ICECS
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015 — conf
Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
LASCAS
Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2015 — conf
Stochastic and topologically aware electromigration analysis for clock skew.
IRPS
Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
2014 A conf
A systematic approach for analyzing and optimizing cell-internal signal electromigration.
ICCAD
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
2014 J jnl
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Palkesh Jain, Frank Cano, Bapana Pudi, N. V. Arvind
2014 J jnl
Design-in-reliability: From library modeling and optimization to gate-level verification.
Microelectron. Reliab.
Palkesh Jain, Bapana Pudi, Meghna Sreenivasan
2012 J jnl
Accurate Current Estimation for Interconnect Reliability Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Palkesh Jain, Ankit Jain
2011 Misc conf
Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects.
VLSI Design
Palkesh Jain, Ankit Jain
2006 Misc conf
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.
VLSI Design
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil