Pai-Yu Chen

25 papers A 5C 4Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2019 J jnl
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures.
IEEE Des. Test
Pai-Yu Chen, Shimeng Yu
2018 — conf
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
ISSCC
Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang
2018 — conf
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons.
ASP-DAC
Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu
2018 J jnl
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2018 J jnl
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2018 — conf
Reliability perspective of resistive synaptic devices on the neuromorphic system performance.
IRPS
Pai-Yu Chen, Shimeng Yu
2018 J jnl
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu
2017 J jnl
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System.
IEEE Trans. Very Large Scale Integr. Syst.
Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti
2017 C conf
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array.
ISCAS
Rui Liu, Pai-Yu Chen, Shimeng Yu
2017 J jnl
Energy-Efficient Adaptive Computing With Multifunctional Memory.
IEEE Trans. Circuits Syst. II Express Briefs
Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu
2016 A conf
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing.
ICCAD
Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu
2016 J jnl
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.
IEEE Trans. Very Large Scale Integr. Syst.
Pai-Yu Chen, Zhiwei Li, Shimeng Yu
2016 J jnl
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning.
IEEE Trans. Multi Scale Comput. Syst.
Pai-Yu Chen, Ligang Gao, Shimeng Yu
2016 C conf
Design of a reliable RRAM-based PUF for compact hardware security primitives.
ISCAS
Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti
2016 A conf
MNSIM: Simulation platform for memristor-based neuromorphic computing system.
DATE
Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang
2016 C conf
Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing.
ISCAS
Pai-Yu Chen, Shimeng Yu
2016 — conf
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM.
ACM Great Lakes Symposium on VLSI
Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia
2015 — conf
Exploiting resistive cross-point array for compact design of physical unclonable function.
HOST
Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu
2015 A conf
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
ICCAD
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2015 J jnl
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2015 C conf
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design.
ISCAS
Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu
2015 A conf
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
DATE
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
2014 A conf
Architecting 3D vertical resistive memory for next-generation storage systems.
ICCAD
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 — conf
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
BioCAS
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
2014 — conf
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity.
BICA
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao