Pablo Abad Fidalgo

20 papers A* 2A 2B 2C 2Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2023 B conf
Performance Characterization of Popular DNN Models on Out-of-Order CPUs.
PACT
Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2022 A conf
Top-Down Performance Profiling on NVIDIA's GPUs.
IPDPS
Alvaro Saiz, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2021 J jnl
Fast, Accurate Processor Evaluation Through Heterogeneous, Sample-Based Benchmarking.
IEEE Trans. Parallel Distributed Syst.
Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2020 B conf
SPECcast: A Methodology for Fast Performance Evaluation with SPEC CPU 2017 Multiprogrammed Workloads.
ICPP
Pablo Prieto, Pablo Abad Fidalgo, Jose Angel Herrero, José-Ángel Gregorio, Valentin Puente
2019 J jnl
Accuracy vs. Computational Cost Tradeoff in Distributed Computer System Simulation.
CoRR
Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2019 A conf
Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms.
IPDPS
Adrian Colaso, Pablo Prieto, Pablo Abad Fidalgo, José-Ángel Gregorio, Valentin Puente
2018 J jnl
Memory Hierarchy Characterization of NoSQL Applications through Full-System Simulation.
IEEE Trans. Parallel Distributed Syst.
Adrian Colaso, Pablo Prieto, Jose Angel Herrero, Pablo Abad Fidalgo, Lucia G. Menezo, Valentin Puente, José-Ángel Gregorio
2018 J jnl
Mosaic: A Scalable Coherence Protocol.
Int. J. Parallel Program.
Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
2016 J jnl
AC-WAR: Architecting the Cache Hierarchy to Improve the Lifetime of a Non-Volatile Endurance-Limited Main Memory.
IEEE Trans. Parallel Distributed Syst.
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2015 J jnl
Improving last level shared cache performance through mobile insertion policies (MIP).
Parallel Comput.
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2013 C conf
Interaction of NoC Design and Coherence Protocol in 3D-Stacked CMPs.
DSD
Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
2013 J jnl
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors.
ACM Trans. Archit. Code Optim.
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2012 J jnl
Adaptive-Tree Multicast: Efficient Multidestination Support for CMP Communication Substrate.
IEEE Trans. Parallel Distributed Syst.
Pablo Abad Fidalgo, Valentin Puente, Lucia G. Menezo, José-Ángel Gregorio
2012 C conf
BIXBAR: A low cost solution to support dynamic link reconfiguration in networks on chip.
ICCD
Pablo Abad Fidalgo, Pablo Prieto, Valentin Puente, José-Ángel Gregorio
2012 J jnl
Balancing Performance and Cost in CMP Interconnection Networks.
IEEE Trans. Parallel Distributed Syst.
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2012 — conf
Improving coherence protocol reactiveness by trading bandwidth for latency.
Conf. Computing Frontiers
Lucia G. Menezo, Valentin Puente, Pablo Abad Fidalgo, José-Ángel Gregorio
2012 — conf
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers.
NOCS
Pablo Abad Fidalgo, Pablo Prieto, Lucia G. Menezo, Adrian Colaso, Valentin Puente, José-Ángel Gregorio
2009 A* conf
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.
HPCA
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2008 — conf
Reducing the Interconnection Network Cost of Chip Multiprocessors.
NOCS
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio
2007 A* conf
Rotary router: an efficient architecture for CMP interconnection networks.
ISCA
Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio, Pablo Prieto