P. V. Ananda Mohan

31 papers C 2Misc 2Journal 23Unranked 4

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	New Generalized Impedance Converter (GIC)-Based Two-Opamp Active RC Biquads. Circuits Syst. Signal Process. P. V. Ananda Mohan
2023	J	`jnl`	Analysis of GIC-Based Frequency-Dependent Negative Resistance-Based Filters. Circuits Syst. Signal Process. P. V. Ananda Mohan
2023	—	`conf`	Hash-based Digital Signatures- A tutorial review. PKIA P. V. Ananda Mohan
2022	—	`conf`	Public Key Cryptographic Implementation Validation: A Review. PKIA P. V. Ananda Mohan, Abey Jacob, Raghavendra S. Patil
2021	J	`jnl`	Evaluation of Mixed-Radix Digit Computation Techniques for the Three Moduli RNS {2 IEEE Trans. Circuits Syst. II Express Briefs P. V. Ananda Mohan, P. S. Phalguna
2020	J	`jnl`	On Actively Compensated Amplifiers Using Negative Impedance Converters. IEEE Trans. Circuits Syst. II Express Briefs P. V. Ananda Mohan
2018	—	`conf`	New Reverse converters for the four-moduli set {2 MWSCAS P. S. Phalguna, Dattaguru V. Kamat, P. V. Ananda Mohan
2018	J	`jnl`	RNS-to-Binary Converters for New Three-Moduli Sets {2k-3, 2k-2, 2k-1} and {2k+1, 2k+2, 2k+3}. J. Circuits Syst. Comput. P. S. Phalguna, Dattaguru V. Kamat, P. V. Ananda Mohan
2018	J	`jnl`	Reverse Converters for the Moduli Set { \(2^{n}, 2^{n-1}-1, 2^{n}-1, 2^{n+1}-1\}(n\, \hbox {Even})\). Circuits Syst. Signal Process. P. V. Ananda Mohan
2017	J	`jnl`	Reverse Conversion Using Core Function, CRT and Mixed Radix Conversion. Circuits Syst. Signal Process. P. V. Ananda Mohan
2016	J	`jnl`	RNS to Binary Conversion Using Diagonal Function and Pirlo and Impedovo Monotonic Function. Circuits Syst. Signal Process. P. V. Ananda Mohan
2015	J	`jnl`	Corrections to "A 0.02 mm IEEE J. Solid State Circuits P. V. Ananda Mohan, Yaohua Zhao, Pui-In Mak, Rui Paulo Martins, Franco Maloberti
2014	J	`jnl`	Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity". IEEE J. Solid State Circuits P. V. Ananda Mohan, Eric A. M. Klumperink, Dlovan H. Mahrof, Bram Nauta
2014	J	`jnl`	Implementation of AES Key Schedule Using Look-Ahead Technique. Circuits Syst. Signal Process. Rashmi R. Rachh, P. V. Ananda Mohan, Basavaraj S. Anami
2013	J	`jnl`	Comments on "Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors". IEEE Trans. Circuits Syst. I Regul. Pap. P. V. Ananda Mohan
2012	J	`jnl`	Efficient Implementations for AES Encryption and Decryption. Circuits Syst. Signal Process. Rashmi R. Rachh, P. V. Ananda Mohan, Basavaraj S. Anami
2011	J	`jnl`	Comments on "Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers". IEEE Trans. Circuits Syst. I Regul. Pap. P. V. Ananda Mohan
2010	J	`jnl`	Novel First-Order and Second-Order Current-Mode Filters Using Multiple-Output Operational Transconductance Amplifiers. Circuits Syst. Signal Process. Dattaguru V. Kamat, P. V. Ananda Mohan, K. Gopalakrishna Prabhu
2010	J	`jnl`	Sensitivity Analysis of Third and Fourth-Order Filters. Circuits Syst. Signal Process. P. V. Ananda Mohan
2007	J	`jnl`	Comments on "A 4th-Order Active- G IEEE J. Solid State Circuits P. V. Ananda Mohan
2005	J	`jnl`	Floating Capacitance Simulation Using Current Conveyors. J. Circuits Syst. Comput. P. V. Ananda Mohan
2003	—	`conf`	Fast implementations of Montgomery's modular multiplication algorithm. ISCAS (4) P. V. Ananda Mohan
1999	J	`jnl`	Efficient Design of Binary to RNS Converters. J. Circuits Syst. Comput. P. V. Ananda Mohan
1996	Misc	`conf`	A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. VLSI Design D. V. Poornaiah, P. V. Ananda Mohan
1995	J	`jnl`	Capacitor Floatation Scheme using only OTAs and Grounded capacitors. J. Circuits Syst. Comput. P. V. Ananda Mohan
1995	Misc	`conf`	Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. VLSI Design D. V. Poornaiah, P. V. Ananda Mohan
1994	C	`conf`	Novel Design for Binary to RNS Converters. ISCAS P. V. Ananda Mohan
1993	C	`conf`	Novel oversampled A/D converters based on error spectrum shaping. ISCAS Y. V. Ramana Rao, P. V. Ananda Mohan
1992	J	`jnl`	Comments on 'New monolithic switched-capacitor differentiators with good noise rejection'. IEEE J. Solid State Circuits P. V. Ananda Mohan
1987	J	`jnl`	New structures for MOSFET-C filters. Proc. IEEE P. V. Ananda Mohan
1985	J	`jnl`	Active filter design using cascaded identical low-order (≥ 2) filter sections. Proc. IEEE P. V. Ananda Mohan