P. Ramakrishna

11 papers C 1Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Design of an optimized parallel hardware architecture for efficient image haze removal.
Multim. Tools Appl.
Harish Babu Gade, Venkata Krishna Odugu, R. Anirudh Reddy, P. Ramakrishna, S. Pothalaiah
2026 J jnl
Optimized 2-D FIR filter bank architecture using various symmetries with parallel processing and DA.
Comput. Electr. Eng.
Venkata Krishna Odugu, P. Ramakrishna, T. Vasudeva Reddy, G. Harish Babu, Janardhanarao S
2025 — conf
7.2: A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET.
ISSCC
Ahmed Mostafa, A. Hassan, A. Hsu, A. K. Singh, C.-H. Wu, C.-R. Yang, D. Prabakaran, Daniel W. Storaska, D. Zhou, Davide Visani, Edmund Hsiao, F. Chu, F. Khan, Fei Lu, G. Cui, G. Wang, J. Natonio, J. Deng, J. Ding, J. Guo, J. Gu, J. Zang, L. Jiang, K.-M. Lu, Mehedi Hasan, M. Kelly, M. H. Kashani, M. Gambhir, M. R. Patoju, M. Singh, M. Shannon, M. Yang, P. Liu, P. Ramakrishna, R. Chen, R. Ho, S. N. Shahi, S. Sivakumar, S. Xu, X. Yang, X. Han, Y.-P. Su, Z. Adal, Z. Guo, Z. Li, Z. Yu, Z. Yan, H. Wang, K. Chang
2025 J jnl
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.
IEEE Solid State Circuits Lett.
Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla
2024 — conf
A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology.
VLSI Technology and Circuits
A. Chowdhury, J. Ma, Y. Li, J. Guo, X. Zhang, P. Ramakrishna, J. Gu, Y. Wang, L. Liang, U. Shukla, K. Mohammad, H. Yan, Y. Sun, M. Lin, Z. Jiang, F. Khan, M. Yeoh, C. Su, J. Ding, Matthew Baecher, S. Parker, H. Wang, M. Seymour, Michael Wielgos, Ken Chang
2024 — conf
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.
VLSI Technology and Circuits
Gautam R. Gangasani, Ahmed Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. Ramakrishna, U. Shukla
2023 J jnl
Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun.
B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha
2023 J jnl
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun.
B. Srikanth, J. V. R. Ravindra, P. Ramakrishna, D. Ajitha
2023 C conf
Governing Equations of Three-Axis Flight Motion Simulator.
CoDIT
Puneet Panwar, Shiju Varghese, S. R. Shimjith, Clement C. Verghese, P. Ramakrishna, P. K. Limaye
2022 — conf
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
ISSCC
Gautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. Ramakrishna, S. Shi, S. Parker, U. Shukla, W. Kelly, W. Su, Z. Yu
2022 J jnl
A low power reconfigurable ADC for bioimpedance monitroing system.
Int. J. Speech Technol.
P. Ramakrishna, K. Hari Kishore