Ozgur Sinanoglu

359 papers A* 11A 46B 13C 27Misc 14Journal 191Unranked 56

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Benchmarking Continual Learning on Netlists with Circuit-Targeted Graph Neural Networks. ASP-DAC Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2026	J	`jnl`	Focus Session: LLM4PQC - An Agentic Framework for Accurate and Efficient Synthesis of PQC Cores. CoRR Buddhi Perera, Zeng Wang, Weihua Xiao, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel, Ramesh Karri
2026	J	`jnl`	GUIDE: GenAI Units In Digital Design Education. CoRR Weihua Xiao, Jason Blocklove, Matthew DeLorenzo, Johann Knechtel, Ozgur Sinanoglu, Kanad Basu, Jeyavijayan Rajendran, Siddharth Garg, Ramesh Karri
2026	J	`jnl`	Graph Neural Networks for Integrated Circuit Design, Reliability, and Security: Survey and Tool. ACM Comput. Surv. Ziad El Sayed, Zeng Wang, Hana Selmani, Johann Knechtel, Ozgur Sinanoglu, Lilas Alrahis
2026	—	`conf`	LLM-Driven Python-to-Rust Translation for Efficient and Safe Code for Neural Networks: llm4py2rs. ICISSP (2) Rupesh Raj Karn, Johann Knechtel, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu
2026	—	`conf`	Securing Hyper-Dimensional Computing: A Locking Mechanism with FPGA Implementation. ICISSP (2) Rupesh Raj Karn, Paul R. Genssler, Hussam Amrouch, Ozgur Sinanoglu
2026	J	`jnl`	Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes. CoRR Weimin Fu, Zeng Wang, Minghao Shao, Ramesh Karri, Muhammad Shafique, Johann Knechtel, Ozgur Sinanoglu, Xiaolong Guo
2026	J	`jnl`	TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening. J. Hardw. Syst. Secur. Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel
2026	J	`jnl`	TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion. CoRR Saideep Sreekumar, Zeng Wang, Akashdeep Saha, Weihua Xiao, Minghao Shao, Muhammad Shafique, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel
2025	—	`conf`	Backdoor Attack Detection in Decision Tree Classifiers Using SHAP Explainability. CAI Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2025	J	`jnl`	DEFending Integrated Circuit Layouts. IEEE Trans. Inf. Forensics Secur. Jitendra Bhandari, Jayanth Gopinath, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri
2025	C	`conf`	Educational Framework for Power Side-Channel Attacks on Neural Networks in Embedded Systems. ISCAS Rupesh Raj Karn, Prithwish Basu Roy, Johann Knechtel, Ozgur Sinanoglu
2025	Misc	`conf`	GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness. VTS Akashdeep Saha, Prithwish Basu Roy, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Lilas Alrahis
2025	A*	`conf`	GlitchFHE: Attacking Fully Homomorphic Encryption Using Fault Injection. USENIX Security Symposium Lakshmi Likhitha Mankali, Mohammed Nabeel, Faiq Raees, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel
2025	C	`conf`	LLM-Driven Code Generation for Neural Networks on FPGAs: Bridging Python and HLS. ICCD Rupesh Raj Karn, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu
2025	—	`conf`	Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper. SOCC Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025	J	`jnl`	Large Language Models (LLMs) for Electronic Design Automation (EDA). CoRR Kangwei Xu, Denis Schwachhofer, Jason Blocklove, Ilia Polian, Peter Domanski, Dirk Pflüger, Siddharth Garg, Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, Zhuorui Zhao, Ulf Schlichtmann, Bing Li
2025	C	`conf`	LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks. ISCAS Jitendra Bhandari, Mohammed Nabeel, Likhitha Mankali, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel
2025	J	`jnl`	LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs. CoRR Akashdeep Saha, Zeng Wang, Prithwish Basu Roy, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri
2025	J	`jnl`	Logic Encryption: This Time for Real. CoRR Rupesh Raj Karn, Lakshmi Likhitha Mankali, Zeng Wang, Saideep Sreekumar, Prithwish Basu Roy, Ozgur Sinanoglu, Lilas Alrahis, Johann Knechtel
2025	—	`conf`	Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation. ICISSP (2) Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2025	J	`jnl`	NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration. CoRR Zeng Wang, Minghao Shao, Akashdeep Saha, Ramesh Karri, Johann Knechtel, Muhammad Shafique, Ozgur Sinanoglu
2025	J	`jnl`	Netlist whisperer: extensive analysis of circuit leakage using LLMs. J. Cryptogr. Eng. Prithwish Basu Roy, Madhav Nair, Rajat Sadhukhan, Manaar Alam, Johann Knechtel, Hammond Pearce, Debdeep Mukhopadhyay, Ozgur Sinanoglu, Ramesh Karri
2025	J	`jnl`	On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning. IEEE Trans. Circuits Syst. I Regul. Pap. Brunno Alves de Abreu, Guilherme Paim, Lilas Alrahis, Paulo F. Flores, Ozgur Sinanoglu, Sergio Bampi, Hussam Amrouch
2025	J	`jnl`	OptiLock: Automated Optimization of Learning-Resilient Logic Locking. IEEE Access Zeng Wang, Lilas Alrahis, Animesh Basak Chowdhury, Dominik Germek, Ramesh Karri, Ozgur Sinanoglu
2025	A	`conf`	RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. DATE Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam, Ramesh Karri, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel
2025	J	`jnl`	SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design. CoRR Zeng Wang, Minghao Shao, Rupesh Raj Karn, Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel
2025	—	`conf`	SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design. MLCAD Zeng Wang, Minghao Shao, Rupesh Raj Karn, Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel
2025	J	`jnl`	SecureX: Strategically Securing Designs Against Oracle-Less Attacks Using GNN-Based Explainers. IEEE Trans. Circuits Syst. I Regul. Pap. Likhitha Mankali, Ozgur Sinanoglu, Satwik Patnaik
2025	J	`jnl`	Targeted Wearout Attacks in Microprocessor Cores. CoRR Joshua Mashburn, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu, Paul V. Gratz
2025	C	`conf`	Trojan Attacks on Graph Convolution Neural Networks for Circuit Analysis. VLSI-SoC Rupesh Raj Karn, Ozgur Sinanoglu
2025	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Trans. Cryptogr. Hardw. Embed. Syst. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2025	J	`jnl`	TrojanLoC: LLM-based Framework for RTL Trojan Localization. CoRR Weihua Xiao, Zeng Wang, Minghao Shao, Raghu Vamshi Hemadri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel, Siddharth Garg, Ramesh Karri
2025	—	`conf`	Unlearning in Decision Tree Classifiers and Microcontroller Implementations. CAI Rupesh Raj Karn, Prithwish Basu Roy, Johann Knechtel, Ozgur Sinanoglu
2025	J	`jnl`	VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination. CoRR Zeng Wang, Minghao Shao, Jitendra Bhandari, Likhitha Mankali, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel
2025	J	`jnl`	VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization. CoRR Zeng Wang, Weihua Xiao, Minghao Shao, Raghu Vamshi Hemadri, Ozgur Sinanoglu, Muhammed Shafique, Ramesh Karri
2025	J	`jnl`	VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding. CoRR Zeng Wang, Minghao Shao, Mohammed Nabeel, Prithwish Basu Roy, Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammed Shafique, Johann Knechtel
2025	J	`jnl`	Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form. CoRR Prithwish Basu Roy, Akashdeep Saha, Manaar Alam, Johann Knechtel, Michail Maniatakos, Ozgur Sinanoglu, Ramesh Karri
2024	A	`conf`	ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. ICCAD Jitendra Bhandari, Animesh Basak Chowdhury, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel
2024	J	`jnl`	ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. CoRR Jitendra Bhandari, Animesh Basak Chowdhury, Mohammed Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri, Johann Knechtel
2024	—	`conf`	Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. ISQED Zhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu
2024	J	`jnl`	Always be Pre-Training: Representation Learning for Network Intrusion Detection with GNNs. CoRR Zhengyao Gu, Diego Troy Lopez, Lilas Alrahis, Ozgur Sinanoglu
2024	—	`conf`	Benchmarking Backdoor Attacks on Graph Convolution Neural Networks: A Comprehensive Analysis of Poisoning Techniques. SPACE Rupesh Raj Karn, Ozgur Sinanoglu
2024	J	`jnl`	Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel
2024	C	`conf`	Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks. IOLTS Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique
2024	J	`jnl`	CircuitHD: Brain-Inspired Hyperdimensional Computing for Circuit Recognition. IEEE Access Paul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch
2024	—	`conf`	Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. ISQED Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. ACM Trans. Archit. Code Optim. Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz, Vassos Soteriou
2024	J	`jnl`	Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability. IEEE Trans. Circuits Syst. I Regul. Pap. Tarek Mohamed, Victor M. van Santen, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch
2024	A	`conf`	HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition. DATE Paul R. Genssler, Lilas Alrahis, Ozgur Sinanoglu, Hussam Amrouch
2024	A*	`conf`	INSIGHT: Attacking Industry-Adopted Learning Resilient Logic Locking Techniques Using Explainable Graph Neural Network. USENIX Security Symposium Lakshmi Likhitha Mankali, Ozgur Sinanoglu, Satwik Patnaik
2024	—	`conf`	LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. ISVLSI Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. CoRR Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	Lightweight Masking Against Static Power Side-Channel Attacks. CoRR Jitendra Bhandari, Mohammed Thari Nabeel, Likhitha Mankali, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel
2024	—	`conf`	Locking Decision Tree with State Permutation Obfuscation: Software Implementation. NewCAS Rupesh Raj Karn, Ozgur Sinanoglu
2024	J	`jnl`	NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack. IACR Cryptol. ePrint Arch. Prithwish Basu Roy, Johann Knechtel, Akashdeep Saha, Saideep Sreekumar, Likhitha Mankali, Mohammed Thari Nabeel, Debdeep Mukhopadhyay, Ramesh Karri, Ozgur Sinanoglu
2024	C	`conf`	Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. ISCAS Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	Progressive Learning With Recurrent Neural Network for Sequence Classification. IEEE Trans. Circuits Syst. II Express Briefs Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation. CoRR Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam, Ramesh Karri, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel
2024	—	`conf`	Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection. APCCAS Jitendra Bhandari, Jayanth Gopinath, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri
2024	Misc	`conf`	Selective Forgetting in Task-Progressive Learning Through Machine Unlearning. ICMLC Rupesh Raj Karn, Johann Knechtel, Ozgur Sinanoglu
2024	C	`conf`	The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security. VLSI-SoC Lilas Alrahis, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu
2024	J	`jnl`	TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel
2024	J	`jnl`	Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini
2023	J	`jnl`	$\tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems. IEEE Trans. Computers Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu
2023	A*	`conf`	ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. DAC Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan
2023	J	`jnl`	ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. CoRR Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan
2023	—	`conf`	AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. DSN-S Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu
2023	J	`jnl`	AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. CoRR Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu
2023	—	`conf`	Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. ISPD Mohammad Eslami, Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri, Samuel Pagliarini
2023	J	`jnl`	Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. IACR Cryptol. ePrint Arch. Jitendra Bhandari, Likhitha Mankali, Mohammed Nabeel, Ozgur Sinanoglu, Ramesh Karri, Johann Knechtel
2023	J	`jnl`	DNN-Alias: Deep Neural Network Protection Against Side-Channel Attacks via Layer Balancing. CoRR Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique
2023	A	`conf`	FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. ISLPED Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique
2023	J	`jnl`	FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation. CoRR Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique
2023	J	`jnl`	FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. IEEE Trans. Emerg. Top. Comput. Swetaki Chatterjee, Nikhil Rangarajan, Satwik Patnaik, Dinesh Rajasekharan, Ozgur Sinanoglu, Yogesh Singh Chauhan
2023	Misc	`conf`	Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? VTS Lilas Alrahis, Ozgur Sinanoglu
2023	J	`jnl`	Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? CoRR Lilas Alrahis, Ozgur Sinanoglu
2023	—	`conf`	Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. ASP-DAC Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu
2023	J	`jnl`	PoisonedGNN: Backdoor Attack on Graph Neural Networks-based Hardware Security Systems. CoRR Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu
2023	J	`jnl`	RESCUE: Resilient, Scalable, High-Corruption, Compact-Key-Set Locking Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nimisha Limaye, Ozgur Sinanoglu
2023	J	`jnl`	SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. IEEE Trans. Neural Networks Learn. Syst. Dinesh Rajasekharan, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Yogesh Singh Chauhan
2023	—	`conf`	Security Closure of IC Layouts Against Hardware Trojans. ISPD Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
2023	—	`conf`	Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs. HCS Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi
2023	C	`conf`	ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules. IOLTS Mahya Morid Ahmadi, Lilas Alrahis, Ozgur Sinanoglu, Muhammad Shafique
2023	J	`jnl`	Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. IEEE Trans. Inf. Forensics Secur. Likhitha Mankali, Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu
2023	C	`conf`	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. ISCAS Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu
2023	J	`jnl`	TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. CoRR Hazem Lashen, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu
2023	—	`conf`	UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. SPACE Lilas Alrahis, Likhitha Mankali, Satwik Patnaik, Abhrajit Sengupta, Johann Knechtel, Ozgur Sinanoglu
2023	J	`jnl`	VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Likhitha Mankali, Satwik Patnaik, Nimisha Limaye, Johann Knechtel, Ozgur Sinanoglu
2023	—	`conf`	X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. ISPD Saideep Sreekumar, Mohammed Ashraf, Mohammed Thari Nabeel, Ozgur Sinanoglu, Johann Knechtel
2022	J	`jnl`	A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. Cryptogr. Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu
2022	J	`jnl`	A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nikhil Rangarajan, Johann Knechtel, Nimisha Limaye, Ozgur Sinanoglu, Hussam Amrouch
2022	J	`jnl`	AntiDOTE: Protecting Debug Against Outsourced Test Entities. IEEE Trans. Emerg. Top. Comput. Nimisha Limaye, Christian Wachsmann, Mohammed Nabeel, Mohammed Ashraf, Arun K. Kanuparthi, Ozgur Sinanoglu
2022	A	`conf`	AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. ICCAD Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch
2022	J	`jnl`	AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks. CoRR Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch
2022	—	`conf`	Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. ISPD Johann Knechtel, Jayanth Gopinath, Mohammed Ashraf, Jitendra Bhandari, Ozgur Sinanoglu, Ramesh Karri
2022	J	`jnl`	Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satwik Patnaik, Mohammed Ashraf, Haocheng Li, Johann Knechtel, Ozgur Sinanoglu
2022	J	`jnl`	Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. Integr. Johann Knechtel, Tarek Ashraf, Natascha Fernengel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Ozgur Sinanoglu, Hussam Amrouch
2022	J	`jnl`	Digitally Assisted Mixed-Signal Circuit Security. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Julian Leonhard, Nimisha Limaye, Shadi Turk, Alhassan Sayed, Alán Rodrigo Díaz Rizo, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. Stratigopoulos
2022	J	`jnl`	Embracing Graph Neural Networks for Hardware Security (Invited Paper). CoRR Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu
2022	A	`conf`	Embracing Graph Neural Networks for Hardware Security. ICCAD Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu
2022	J	`jnl`	GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lilas Alrahis, Abhrajit Sengupta, Johann Knechtel, Satwik Patnaik, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2022	J	`jnl`	GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. CoRR Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu
2022	J	`jnl`	GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu
2022	J	`jnl`	GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking. IEEE Trans. Emerg. Top. Comput. Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique, Ozgur Sinanoglu
2022	J	`jnl`	Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. CoRR Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu
2022	J	`jnl`	Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. IEEE Comput. Archit. Lett. Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz
2022	J	`jnl`	Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. CoRR Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz
2022	J	`jnl`	Hide & Seek: Seeking the (Un)-Hidden key in Provably-Secure Logic Locking Techniques. CoRR Satwik Patnaik, Nimisha Limaye, Ozgur Sinanoglu
2022	J	`jnl`	Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques. IEEE Trans. Inf. Forensics Secur. Satwik Patnaik, Nimisha Limaye, Ozgur Sinanoglu
2022	J	`jnl`	IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism. IACR Cryptol. ePrint Arch. Shaza Elsharief, Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu
2022	A	`conf`	MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. DATE Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu
2022	B	`conf`	NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. IJCNN Mahya Morid Ahmadi, Lilas Alrahis, Alessio Colucci, Ozgur Sinanoglu, Muhammad Shafique
2022	J	`jnl`	NeuroUnlock: Unlocking the Architecture of Obfuscated Deep Neural Networks. CoRR Mahya Morid Ahmadi, Lilas Alrahis, Alessio Colucci, Ozgur Sinanoglu, Muhammad Shafique
2022	J	`jnl`	OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking. IEEE Trans. Circuits Syst. II Express Briefs Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu
2022	J	`jnl`	Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. IEEE Trans. Emerg. Top. Comput. Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja
2022	J	`jnl`	PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans. IEEE Trans. Emerg. Top. Comput. Nimisha Limaye, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Kanad Basu
2022	—	`conf`	SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu
2022	J	`jnl`	Security Closure of IC Layouts Against Hardware Trojans. CoRR Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
2022	J	`jnl`	Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits. IEEE Trans. Emerg. Top. Comput. Shubham Rai, Satwik Patnaik, Ansh Rupani, Johann Knechtel, Ozgur Sinanoglu, Akash Kumar
2022	J	`jnl`	SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. IEEE Embed. Syst. Lett. Nikhil Rangarajan, Johann Knechtel, Dinesh Rajasekharan, Ozgur Sinanoglu
2022	J	`jnl`	Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques. IEEE Trans. Inf. Forensics Secur. Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu
2022	J	`jnl`	X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. CoRR Saideep Sreekumar, Mohammed Ashraf, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel
2021	J	`jnl`	A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. IEEE Trans. Emerg. Top. Comput. Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2021	J	`jnl`	Breaking CAS-Lock and Its Variants by Exploiting Structural Traces. IACR Cryptol. ePrint Arch. Abhrajit Sengupta, Nimisha Limaye, Ozgur Sinanoglu
2021	J	`jnl`	Breaking CAS-Lock and Its Variants by Exploiting Structural Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. Abhrajit Sengupta, Nimisha Limaye, Ozgur Sinanoglu
2021	J	`jnl`	Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young
2021	A	`conf`	Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques. DATE Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu
2021	A*	`conf`	Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. DAC Nimisha Limaye, Animesh Basak Chowdhury, Christian Pilato, Mohammed Thari Nabeel, Ozgur Sinanoglu, Siddharth Garg, Ramesh Karri
2021	A	`conf`	GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. DATE Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique, Ozgur Sinanoglu
2021	J	`jnl`	Guest Editorial: Special Issue On Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. Ozgur Sinanoglu, Ümit Y. Ogras
2021	J	`jnl`	Interposer-Based Root of Trust. CoRR Tapojyoti Mandal, Gino Chacon, Johann Knechtel, Ozgur Sinanoglu, Paul Gratz, Vassos Soteriou
2021	J	`jnl`	MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. CoRR Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu
2021	J	`jnl`	ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. IEEE Trans. Emerg. Top. Comput. Lilas Alrahis, Muhammad Yasin, Nimisha Limaye, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2021	A	`conf`	Security Closure of Physical Layouts ICCAD Special Session Paper. ICCAD Johann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri
2021	J	`jnl`	Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nimisha Limaye, Emmanouil Kalligeros, Nikolaos Karousos, Irene G. Karybali, Ozgur Sinanoglu
2021	A	`conf`	Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. ICCAD Jens Lienig, Susann Rothe, Matthias Thiele, Nikhil Rangarajan, Mohammed Ashraf, Mohammed Nabeel, Hussam Amrouch, Ozgur Sinanoglu, Johann Knechtel
2021	J	`jnl`	UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. IEEE Trans. Inf. Forensics Secur. Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2021	A	`conf`	UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. ICCAD Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu
2021	J	`jnl`	UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. CoRR Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, Ozgur Sinanoglu
2020	J	`jnl`	2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. CoRR Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel
2020	J	`jnl`	2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. IEEE Trans. Computers Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel
2020	J	`jnl`	Attacking Split Manufacturing from a Deep Learning Perspective. CoRR Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2020	J	`jnl`	Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. CoRR Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020	B	`conf`	Design Obfuscation versus Test. ETS Farimah Farahmandi, Ozgur Sinanoglu, Ronald D. Blanton, Samuel Pagliarini
2020	A	`conf`	DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. DATE Nimisha Limaye, Ozgur Sinanoglu
2020	J	`jnl`	DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys. CoRR Nimisha Limaye, Ozgur Sinanoglu
2020	J	`jnl`	GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. CoRR Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani Saleh, Muhammad Shafique, Ozgur Sinanoglu
2020	J	`jnl`	Guest Editors' Introduction: Special Issue on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. Ozgur Sinanoglu, Ümit Y. Ogras
2020	J	`jnl`	Keynote: A Disquisition on Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhishek Chakraborty, Nithyashankari Gummidipoondi Jayasankaran, Yuntao Liu, Jeyavijayan Rajendran, Ozgur Sinanoglu, Ankur Srivastava, Yang Xie, Muhammad Yasin, Michael Zuzak
2020	J	`jnl`	Logic Locking With Provable Security Against Power Analysis Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhrajit Sengupta, Bodhisatwa Mazumdar, Muhammad Yasin, Ozgur Sinanoglu
2020	J	`jnl`	Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2020	J	`jnl`	Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2020	J	`jnl`	Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). CoRR Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
2020	J	`jnl`	Power Side-Channel Attacks in Negative Capacitance Transistor. IEEE Micro Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
2020	J	`jnl`	Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Trans. Emerg. Top. Comput. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2020	J	`jnl`	SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. IEEE Access Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2020	J	`jnl`	Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2020	J	`jnl`	Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhrajit Sengupta, Mohammed Nabeel, Nimisha Limaye, Mohammed Ashraf, Ozgur Sinanoglu
2020	—	`book`	Trustworthy Hardware Design: Combinational Logic Locking Techniques Muhammad Yasin, Jeyavijayan Rajendran, Ozgur Sinanoglu
2020	J	`jnl`	UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. CoRR Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2019	C	`conf`	3D Integration: Another Dimension Toward Hardware Security. IOLTS Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu
2019	J	`jnl`	3D Integration: Another Dimension Toward Hardware Security. CoRR Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu
2019	J	`jnl`	A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. CoRR Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2019	A	`conf`	A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. DATE Abhrajit Sengupta, Mohammed Nabeel, Johann Knechtel, Ozgur Sinanoglu
2019	J	`jnl`	A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. CoRR Abhrajit Sengupta, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu
2019	J	`jnl`	An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. CoRR Mohammed Nabeel, Mohammed Ashraf, Satwik Patnaik, Vassos Soteriou, Ozgur Sinanoglu, Johann Knechtel
2019	A*	`conf`	Attacking Split Manufacturing from a Deep Learning Perspective. DAC Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
2019	J	`jnl`	CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist. IACR Cryptol. ePrint Arch. Abhrajit Sengupta, Ozgur Sinanoglu
2019	J	`jnl`	Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design. IEEE Trans. Emerg. Top. Comput. Ozgur Sinanoglu, Omer Khan
2019	A	`conf`	Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. ICCAD Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu
2019	J	`jnl`	Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access. CoRR Nimisha Limaye, Abhrajit Sengupta, Mohammed Nabeel, Ozgur Sinanoglu
2019	—	`conf`	Logic Locking of Boolean Circuits: Provable Hardware-Based Obfuscation from a Tamper-Proof Memory. SECITC Giovanni Di Crescenzo, Abhrajit Sengupta, Ozgur Sinanoglu, Muhammad Yasin
2019	A	`conf`	MixLock: Securing Mixed-Signal Circuits via Logic Locking. DATE Julian Leonhard, Muhammad Yasin, Shadi Turk, Mohammed Thari Nabeel, Marie-Minerve Louërat, Roselyne Chotin-Avot, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos
2019	—	`conf`	Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application. SMACD Julian Leonhard, Marie-Minerve Louërat, Hassan Aboushady, Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos
2019	—	`conf`	Protect Your Chip Design Intellectual Property: An Overview. COINS Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu
2019	J	`jnl`	Protect Your Chip Design Intellectual Property: An Overview. CoRR Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu
2019	B	`conf`	Revisiting Logic Locking for Reversible Computing. ETS Nimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu
2019	J	`jnl`	SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. CoRR Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2019	J	`jnl`	ScanSAT: Unlocking Obfuscated Scan Chains. IACR Cryptol. ePrint Arch. Lilas Alrahis, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2019	J	`jnl`	ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. CoRR Lilas Alrahis, Muhammad Yasin, Nimisha Limaye, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2019	—	`conf`	ScanSAT: unlocking obfuscated scan chains. ASP-DAC Lilas Alrahis, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu
2019	J	`jnl`	Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. IEEE Des. Test Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2019	J	`jnl`	Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. CoRR Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2019	J	`jnl`	Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) - Unlocked. IEEE Trans. Inf. Forensics Secur. Fangfei Yang, Ming Tang, Ozgur Sinanoglu
2019	J	`jnl`	Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. CoRR Johann Knechtel, Jacek Gosciniak, Alabi Bojesomo, Satwik Patnaik, Ozgur Sinanoglu, Mahmoud Rasras
2018	Misc	`conf`	ATPG-based cost-effective, secure logic locking. VTS Abhrajit Sengupta, Mohammed Thari Nabeel, Muhammad Yasin, Ozgur Sinanoglu
2018	J	`jnl`	Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices. CoRR Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2018	A	`conf`	Advancing hardware security using polymorphic and stochastic spin-hall effect devices. DATE Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja
2018	J	`jnl`	Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs. CoRR Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2018	A	`conf`	Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. ICCAD Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel
2018	J	`jnl`	Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. CoRR Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu
2018	—	`conf`	Concerted wire lifting: Enabling secure and cost-effective split manufacturing. ASP-DAC Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu
2018	A	`conf`	Customized locking of IP blocks on a multi-million-gate SoC. ICCAD Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Ozgur Sinanoglu
2018	J	`jnl`	Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. CoRR Nikhil Rangarajan, Satwik Patnaik, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Shaloo Rakheja
2018	J	`jnl`	Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL. CoRR Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu
2018	A*	`conf`	Raise your game for split manufacturing: restoring the true functionality through BEOL. DAC Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu
2018	A	`conf`	Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition. ITC Muhammad Yasin, Ozgur Sinanoglu
2018	A	`conf`	Towards provably-secure performance locking. DATE Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran
2017	J	`jnl`	A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. IEEE Des. Test Samah Mohamed Saeed, Ozgur Sinanoglu
2017	J	`jnl`	Adaptive Reduction of the Frequency Search Space for Multi-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu
2017	C	`conf`	Evolution of logic locking. VLSI-SoC Muhammad Yasin, Ozgur Sinanoglu
2017	J	`jnl`	Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities. IEEE Trans. Emerg. Top. Comput. Swarup Bhunia, An Chen, Ozgur Sinanoglu, Jason M. Fung
2017	J	`jnl`	Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. IPSJ Trans. Syst. LSI Des. Methodol. Johann Knechtel, Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Jens Lienig, Cliff C. N. Sze
2017	J	`jnl`	Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. CoRR Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu
2017	A	`conf`	Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. ICCAD Satwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu
2017	A*	`conf`	On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. DAC Johann Knechtel, Ozgur Sinanoglu
2017	J	`jnl`	On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. CoRR Johann Knechtel, Ozgur Sinanoglu
2017	A	`ed.`	Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, AsiaCCS 2017, Abu Dhabi, United Arab Emirates, April 2-6, 2017 AsiaCCS Ramesh Karri, Ozgur Sinanoglu, Ahmad-Reza Sadeghi, Xun Yi
2017	A*	`conf`	Provably-Secure Logic Locking: From Theory To Practice. CCS Muhammad Yasin, Abhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Jeyavijayan Rajendran, Ozgur Sinanoglu
2017	J	`jnl`	Removal Attacks on Logic Locking and Camouflaging Techniques. IACR Cryptol. ePrint Arch. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	J	`jnl`	Rethinking Split Manufacturing: An Information-Theoretic Approach with Secure Layout Techniques. CoRR Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu
2017	A	`conf`	Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. ICCAD Abhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu
2017	—	`conf`	Security analysis of Anti-SAT. ASP-DAC Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	—	`conf`	TTLock: Tenacious and traceless logic locking. HOST Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
2017	J	`jnl`	Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Trans. Inf. Forensics Secur. Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
2017	J	`jnl`	Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. IEEE Trans. Emerg. Top. Comput. Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
2017	J	`jnl`	Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases. IEEE Trans. Circuits Syst. I Regul. Pap. Muhammad Yasin, Temesghen Tekeste, Hani Saleh, Baker Mohammad, Ozgur Sinanoglu, Mohammed Ismail
2017	—	`conf`	What to Lock?: Functional and Parametric Locking. ACM Great Lakes Symposium on VLSI Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	J	`jnl`	A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities. ACM Trans. Design Autom. Electr. Syst. Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2016	J	`jnl`	A Comparative Security Analysis of Current and Emerging Technologies. IEEE Micro Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2016	A	`conf`	Activation of logic encrypted chips: Pre-test or post-test? DATE Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu
2016	J	`jnl`	Adapting to Varying Distribution of Unknown Response Bits. ACM Trans. Design Autom. Electr. Syst. Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev
2016	J	`jnl`	Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Trans. Very Large Scale Integr. Syst. Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
2016	A	`conf`	CamoPerturb: secure IC camouflaging for minterm protection. ICCAD Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	—	`conf`	Do you trust your chip? DTIS Ozgur Sinanoglu
2016	J	`jnl`	Guest Editorial Special Issue on Secure and Trustworthy Computing. ACM J. Emerg. Technol. Comput. Syst. Ozgur Sinanoglu, Ramesh Karri
2016	—	`conf`	Microfluidic encryption of on-chip biochemical assays. BioCAS Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri
2016	J	`jnl`	On Improving the Security of Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
2016	C	`conf`	Power-side-channel analysis of carbon nanotube FET based design. IOLTS Chandra K. H. Suresh, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2016	—	`conf`	SARLock: SAT attack resistant logic locking. HOST Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
2016	J	`jnl`	Security Analysis of Anti-SAT. IACR Cryptol. ePrint Arch. Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	J	`jnl`	Security Assessment of Cyberphysical Digital Microfluidic Biochips. IEEE ACM Trans. Comput. Biol. Bioinform. Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri
2016	J	`jnl`	Supply-Chain Security of Digital Microfluidic Biochips. Computer Sk Subidh Ali, Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, Krishnendu Chakrabarty
2016	J	`jnl`	Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging. IACR Cryptol. ePrint Arch. Muhammad Yasin, Ozgur Sinanoglu, Jeyavijayan Rajendran
2016	Misc	`conf`	Thwarting timing attacks on NEMS relay based designs. VTS Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu
2015	C	`conf`	A secure design-for-test infrastructure for lifetime security of SoCs. ISCAS Jerry Backer, Sk Subidh Ali, Kurt Rosenfeld, David Hély, Ozgur Sinanoglu, Ramesh Karri
2015	J	`jnl`	Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation. ACM Trans. Design Autom. Electr. Syst. Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu
2015	J	`jnl`	Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri
2015	J	`jnl`	Fault Analysis-Based Logic Encryption. IEEE Trans. Computers Jeyavijayan Rajendran, Huan Zhang, Chi Zhang, Garrett S. Rose, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2015	J	`jnl`	Guest Editorial Special Section on Hardware Security and Trust. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia
2015	J	`jnl`	MAGIC: Malicious Aging in Circuits/Cores. ACM Trans. Archit. Code Optim. Naghmeh Karimi, Arun Karthik Kanuparthi, Xueyang Wang, Ozgur Sinanoglu, Ramesh Karri
2015	J	`jnl`	Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu
2015	J	`jnl`	Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2015	C	`conf`	Power analysis attacks on ARX: An application to Salsa20. IOLTS Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2015	—	`conf`	Scan attack on Elliptic Curve Cryptosystem. DFTS Sk Subidh Ali, Ozgur Sinanoglu
2015	J	`jnl`	Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri
2015	—	`conf`	Security analysis of logic encryption against the most effective side-channel attack: DPA. DFTS Muhammad Yasin, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2015	C	`conf`	Security implications of cyberphysical digital microfluidic biochips. ICCD Sk Subidh Ali, Mohamed Ibrahim, Ozgur Sinanoglu, Krishnendu Chakrabarty, Ramesh Karri
2015	Misc	`conf`	TMO: A new class of attack on cipher misusing test infrastructure. VTS Sk Subidh Ali, Ozgur Sinanoglu
2015	C	`conf`	Timing attack on NEMS relay based design of AES. VLSI-SoC Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu
2015	—	`conf`	Transforming between logic locking and IC camouflaging. IDT Muhammad Yasin, Ozgur Sinanoglu
2014	C	`conf`	AES design space exploration new line for scan attack resiliency. VLSI-SoC Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
2014	A	`conf`	Approximating the age of RF/analog circuits through re-characterization and statistical estimation. DATE Doohwang Chang, Sule Ozev, Ozgur Sinanoglu, Ramesh Karri
2014	J	`jnl`	Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Ozgur Sinanoglu
2014	Misc	`conf`	Detection, diagnosis, and repair of faults in memristor-based memories. VTS Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu
2014	—	`conf`	New scan attacks against state-of-the-art countermeasures and DFT. HOST Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
2014	J	`jnl`	Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2014	A*	`conf`	Secure Memristor-based Main Memory. DAC Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu
2014	—	`conf`	Slack removal for enhanced reliability and trust. DTIS Abishek Ramdas, Samah Mohamed Saeed, Ozgur Sinanoglu
2014	A	`conf`	Test-mode-only scan attack and countermeasure for contemporary scan architectures. ITC Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
2014	B	`conf`	Test-mode-only scan attack using the boundary scan chain. ETS Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri
2013	A	`conf`	Adaptive reduction of the frequency search space for multi-vdd digital circuits. DATE Chandra K. H. Suresh, Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu
2013	J	`jnl`	Eliminating the Timing Penalty of Scan. J. Electron. Test. Ozgur Sinanoglu, Vishwani D. Agrawal
2013	—	`conf`	Embedded tutorial: Regaining hardware security and trust. LATW Ozgur Sinanoglu
2013	J	`jnl`	Expedited-compact architecture for average scan power reduction. IEEE Des. Test Samah Mohamed Saeed, Ozgur Sinanoglu
2013	C	`conf`	High-level synthesis for security and trust. IOLTS Jeyavijayan Rajendran, Huan Zhang, Ozgur Sinanoglu, Ramesh Karri
2013	A	`conf`	Is split manufacturing secure? DATE Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2013	—	`conf`	New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. VLSI-SoC (Selected Papers) Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2013	C	`conf`	New scan-based attack using only the test mode. VLSI-SoC Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri
2013	J	`jnl`	Predictive Techniques for Projecting Test Data Volume Compression. IEEE Trans. Very Large Scale Integr. Syst. Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim
2013	B	`conf`	Reconciling the IC test and security dichotomy. ETS Ozgur Sinanoglu, Naghmeh Karimi, Jeyavijayan Rajendran, Ramesh Karri, Yier Jin, Ke Huang, Yiorgos Makris
2013	J	`jnl`	Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints. J. Electron. Test. Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu
2013	C	`conf`	Scan attack in presence of mode-reset countermeasure. IOLTS Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri
2013	J	`jnl`	Scan to Nonscan Conversion via Test Cube Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ozgur Sinanoglu
2013	A*	`conf`	Security analysis of integrated circuit camouflaging. CCS Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, Ramesh Karri
2013	C	`conf`	Sneak path testing and fault modeling for multilevel memristor-based memories. ICCD Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu
2013	Misc	`conf`	Sneak-path Testing of Memristor-based Memories. VLSI Design Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
2013	J	`jnl`	Testing Chips With Spare Identical Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abishek Ramdas, Ozgur Sinanoglu
2013	A	`conf`	VLSI testing based security metric for IC camouflaging. ITC Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri
2012	B	`conf`	Adaptive testing of chips with varying distributions of unknown response bits. ETS Chandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev
2012	B	`conf`	Adaptive testing: Conquering process variations. ETS Ender Yilmaz, Sule Ozev, Ozgur Sinanoglu, Peter C. Maxwell
2012	J	`jnl`	An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks. Comput. J. Mehmet Hakan Karaata, Ozgur Sinanoglu, Bader F. AlBdaiwi
2012	B	`conf`	DfT support for launch and capture power reduction in launch-off-capture testing. ETS Samah Mohamed Saeed, Ozgur Sinanoglu
2012	Misc	`conf`	Eliminating Performance Penalty of Scan. VLSI Design Ozgur Sinanoglu
2012	C	`conf`	Engineering crossbar based emerging memory technologies. ICCD Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu
2012	J	`jnl`	Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits. Comput. J. Ozgur Sinanoglu
2012	A	`conf`	Logic encryption: A fault analysis perspective. DATE Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2012	J	`jnl`	Multi-modal response compaction adaptive to x-density variation. IET Comput. Digit. Tech. Samah Mohamed Saeed, Ozgur Sinanoglu
2012	—	`conf`	Retiming scan circuit to eliminate timing penalty. LATW Ozgur Sinanoglu, Vishwani D. Agrawal
2012	A*	`conf`	Security analysis of logic obfuscation. DAC Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri
2012	C	`conf`	Test access mechanism for chips with spare identical cores. IOLTS Ozgur Sinanoglu
2012	B	`conf`	Toggle-masking scheme for x-filtering. ETS Abishek Ramdas, Ozgur Sinanoglu
2011	Misc	`conf`	Design and analysis of ring oscillator based Design-for-Trust technique. VTS Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri
2011	J	`jnl`	Enhancing encoding capacity of combinational test stimulus decompressors. Sci. China Inf. Sci. Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla
2011	—	`conf`	Error-resilient design of branch predictors for effective yield improvement. LATW Sobeeh Almukhaizim, Ozgur Sinanoglu
2011	Misc	`conf`	Expedited response compaction for scan power reduction. VTS Samah Mohamed Saeed, Ozgur Sinanoglu
2011	J	`jnl`	Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits. IET Comput. Digit. Tech. Sobeeh Almukhaizim, Ozgur Sinanoglu
2011	Misc	`conf`	Revival of partial scan: Test cube analysis driven conversion of flip-flops. VTS Nader Alawadhi, Ozgur Sinanoglu
2011	—	`conf`	Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing. Asian Test Symposium Ozgur Sinanoglu
2011	J	`jnl`	Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits. J. Low Power Electron. Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu
2011	—	`conf`	Test power reduction via deterministic alignment of stimulus and response bits. LATW Sobeeh Almukhaizim, Eman AlQuraishi, Ozgur Sinanoglu
2011	B	`conf`	Toggle-Based Masking Scheme for Clustered Unknown Response Bits. ETS Ozgur Sinanoglu
2011	J	`jnl`	Unified 2-D X-Alignment for Improving the Observability of Response Compactors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ozgur Sinanoglu, Sobeeh Almukhaizim
2010	B	`conf`	Add-on blocks and algorithms for improving stimulus compression. ETS Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla
2010	J	`jnl`	An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks. IEEE Trans. Computers Ozgur Sinanoglu, Mehmet Hakan Karaata, Bader F. AlBdaiwi
2010	—	`conf`	Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG. IDT Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim
2010	J	`jnl`	On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power. J. Electron. Test. Sobeeh Almukhaizim, Shouq Alsubaihi, Ozgur Sinanoglu
2010	—	`conf`	Pattern Encodability Enhancements for Test Stimulus Decompressors. Asian Test Symposium Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla
2010	A	`conf`	Predictive analysis for projecting test compression levels. ITC Ozgur Sinanoglu, Sobeeh Almukhaizim
2010	B	`conf`	Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. ETS Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu
2010	—	`conf`	Reconfigurable low-power Concurrent Error Detection in logic circuits. IDT Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu
2010	C	`conf`	Reconfigurable low-power Concurrent Error Detection in logic circuits. IOLTS Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu
2010	—	`conf`	XOR-Based Response Compactor Adaptive to X-Density Variation. Asian Test Symposium Samah Mohamed Saeed, Ozgur Sinanoglu
2009	J	`jnl`	Align-Encode Delay Assignment in the Case of XOR-Decompressors: Impact of Parallel Computations. J. Interconnect. Networks Mohammed Al-Mulla, Ozgur Sinanoglu, Mohammed Nael Taha, Nader Alawadhi
2009	J	`jnl`	Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sobeeh Almukhaizim, Ozgur Sinanoglu
2009	—	`conf`	Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments. DFT Nader Alawadhi, Ozgur Sinanoglu
2009	J	`jnl`	Scan Cell Positioning for Boosting the Compression of Fan-Out Networks. J. Comput. Sci. Technol. Ozgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu
2009	J	`jnl`	Scan Chain Hold-Time Violations: Can They be Tolerated? IEEE Trans. Very Large Scale Integr. Syst. Ozgur Sinanoglu, Philip Schremmer
2009	J	`jnl`	Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Des. Test Comput. Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick
2009	J	`jnl`	Utilisation of inverse compatibility for test cost reductions. IET Comput. Digit. Tech. Ozgur Sinanoglu, Mohammed Al-Mulla, Mohammed Nael Taha
2009	J	`jnl`	X-Align: Improving the Scan Cell Observability of Response Compactors. IEEE Trans. Very Large Scale Integr. Syst. Ozgur Sinanoglu, Sobeeh Almukhaizim
2009	A	`conf`	X-alignment techniques for improving the observability of response compactors. ITC Ozgur Sinanoglu, Sobeeh Almukhaizim
2008	A	`conf`	Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors. ITC Ozgur Sinanoglu
2008	A	`conf`	Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing. DATE Ozgur Sinanoglu, Erik Jan Marinissen
2008	J	`jnl`	Construction of an adaptive scan network for test time and data volume reduction. IET Comput. Digit. Tech. Ozgur Sinanoglu
2008	J	`jnl`	Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells. J. Electron. Test. Ozgur Sinanoglu
2008	J	`jnl`	Isolation Techniques for Soft Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ozgur Sinanoglu, Tsvetomir Petrov
2008	A	`conf`	Peak Power Reduction Through Dynamic Partitioning of Scan Chains. ITC Sobeeh Almukhaizim, Ozgur Sinanoglu
2008	J	`jnl`	Scan Architecture With Align-Encode. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ozgur Sinanoglu
2008	J	`jnl`	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. J. Electron. Test. Ozgur Sinanoglu
2007	A	`conf`	A non-intrusive isolation approach for soft cores. DATE Ozgur Sinanoglu, Tsvetomir Petrov
2007	A	`conf`	Diagnosis, modeling and tolerance of scan chain hold-time violations. DATE Ozgur Sinanoglu, Philip Schremmer
2007	J	`jnl`	Low Cost Scan Test by Test Correlation Utilization. J. Comput. Sci. Technol. Ozgur Sinanoglu
2005	J	`jnl`	Efficient RT-Level Fault Diagnosis. J. Comput. Sci. Technol. Ozgur Sinanoglu, Alex Orailoglu
2005	J	`jnl`	Test power reductions through computationally efficient, decoupled scan chain modifications. IEEE Trans. Reliab. Ozgur Sinanoglu, Alex Orailoglu
2004	A	`conf`	Autonomous Yet Deterministic Test of SOC Cores. ITC Ozgur Sinanoglu, Alex Orailoglu
2004	—	`conf`	Efficient RT-level fault diagnosis methodology. ASP-DAC Ozgur Sinanoglu, Alex Orailoglu
2004	C	`conf`	Extending the Applicability of Parallel-Serial Scan Designs. ICCD Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
2004	J	`jnl`	Fast and energy-frugal deterministic test through efficient compression and compaction techniques. J. Syst. Archit. Ozgur Sinanoglu, Alex Orailoglu
2004	B	`conf`	Pipelined test of SOC cores through test data transformations. ETS Ozgur Sinanoglu, Alex Orailoglu
2004	A	`conf`	Scan Power Minimization through Stimulus and Response Transformations. DATE Ozgur Sinanoglu, Alex Orailoglu
2003	C	`conf`	Aggressive Test Power Reduction Through Test Stimuli Transformation. ICCD Ozgur Sinanoglu, Alex Orailoglu
2003	J	`jnl`	Compacting Test Responses for Deeply Embedded SoC Cores. IEEE Des. Test Comput. Ozgur Sinanoglu, Alex Orailoglu
2003	C	`conf`	Hierarchical Constraint Conscious RT-level Test Generation. DSD Ozgur Sinanoglu, Alex Orailoglu
2003	A	`conf`	Modeling Scan Chain Modifications For Scan-in Test Power Minimization. ITC Ozgur Sinanoglu, Alex Orailoglu
2003	—	`conf`	Parity-based output compaction for core-based SOCs [logic testing]. ETW Ozgur Sinanoglu, Alex Orailoglu
2003	A	`conf`	Partial Core Encryption for Performance-Efficient Test of SOCs. ICCAD Ozgur Sinanoglu, Alex Orailoglu
2003	J	`jnl`	Reducing Average and Peak Test Power Through Scan Chain Modification. J. Electron. Test. Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2003	—	`conf`	Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test. Asian Test Symposium Ozgur Sinanoglu, Alex Orailoglu
2002	A	`conf`	A novel scan architecture for power-efficient, rapid test. ICCAD Ozgur Sinanoglu, Alex Orailoglu
2002	—	`conf`	Dynamic test data transformations for average and peak power reductions. ETW Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002	J	`jnl`	Efficient Construction of Aliasing-Free Compaction Circuitry. IEEE Micro Ozgur Sinanoglu, Alex Orailoglu
2002	—	`conf`	Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation. DFT Ozgur Sinanoglu, Alex Orailoglu
2002	A	`conf`	Scan Power Reduction Through Test Data Transition Frequency Analysis. ITC Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002	Misc	`conf`	Test Power Reduction through Minimization of Scan Chain Transitions. VTS Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2001	—	`conf`	Compaction Schemes with Minimum Test Application Time. Asian Test Symposium Ozgur Sinanoglu, Alex Orailoglu
2001	Misc	`conf`	RT-level Fault Simulation Based on Symbolic Propagation. VTS Ozgur Sinanoglu, Alex Orailoglu
2001	A	`conf`	Space and time compaction schemes for embedded cores. ITC Ozgur Sinanoglu, Alex Orailoglu