Oswaldo Cadenas

20 papers B 3C 3Misc 3Journal 4Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
Non-uniform quantization with linear average-case computation time.
CoRR
Oswaldo Cadenas, Graham M. Megson
2019 J jnl
Running Median Algorithm and Implementation for Integer Streaming Applications.
IEEE Embed. Syst. Lett.
Oswaldo Cadenas, Graham M. Megson
2015 — conf
Objective Empirical Mode Decomposition metric.
TSP
Dawid Laszuk, Oswaldo Cadenas, Slawomir J. Nasuto
2014 Misc conf
Acceleration and visualization of Dynamic Network Optimization.
ICNC
Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson
2013 — conf
Asynchronous distributed parallelization of mobile network optimization algorithms.
VITAE
Yuanzhou Ye, Graham M. Megson, Oswaldo Cadenas
2013 Misc conf
Distributed parallelization of greedy Mobile Network Optimization algorithms.
SoftCOM
Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson
2006 B conf
Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.
FPL
Oswaldo Cadenas, Graham M. Megson
2005 — conf
A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation.
ISVLSI
Oswaldo Cadenas, Graham M. Megson, Daniel Jones
2005 J jnl
A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers.
IEEE Trans. Consumer Electron.
Robert Simon Sherratt, Oswaldo Cadenas, Nomita Goswami
2005 — conf
FPGA Organization for the Fast Path-Based Neural Branch Predictor.
FPT
Oswaldo Cadenas, Graham M. Megson, Daniel Jones
2005 C conf
Implementation of a block based neural branch predictor.
DSD
Oswaldo Cadenas, Graham M. Megson, Daniel Jones
2004 — conf
A FPGA pipelined backward adaptive scalar quantizer.
Circuits, Signals, and Systems
Oswaldo Cadenas, Graham M. Megson
2004 J jnl
A clocking technique for FPGA pipelined designs.
J. Syst. Archit.
Oswaldo Cadenas, Graham M. Megson
2003 — conf
FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture.
Engineering of Reconfigurable Systems and Algorithms
Oswaldo Cadenas, Graham M. Megson, Toomas P. Plaks
2003 — conf
Pullpipelining: A technique for systolic pipelined circuits.
IWSOC
Oswaldo Cadenas, Graham M. Megson
2002 B conf
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.
FPL
Oswaldo Cadenas, Graham M. Megson
2002 C conf
Improving mW/MHz Ratio in FPGAs Pipelined Designs.
DSD
Oswaldo Cadenas, Graham M. Megson
2001 B conf
A n-Bit Reconfigurable Scalar Quantiser.
FPL
Oswaldo Cadenas, Graham M. Megson
2001 C conf
Pipelining Considerations for an FPGA Case.
DSD
Oswaldo Cadenas, Graham M. Megson
1999 Misc conf
Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods.
PDPTA
Toomas P. Plaks, Oswaldo Cadenas, Graham M. Megson