Oscar Ruano - RankMe

16 papers C 2Journal 14

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications. IEEE Trans. Computers Daniel Báscones, Francisco Garcia-Herrero, Oscar Ruano, Carlos González, Daniel Mozos, Juan Antonio Maestro
2024	J	`jnl`	Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration. IEEE Trans. Circuits Syst. II Express Briefs José Luis Imaña, Luis Piñuel, Yao-Ming Kuo, Oscar Ruano, Francisco Garcia-Herrero
2023	J	`jnl`	Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2023	J	`jnl`	RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2022	J	`jnl`	ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2022	J	`jnl`	Design and implementation of efficient QCA full-adders using fault-tolerant majority gates. J. Supercomput. Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián, Oscar Ruano, Francisco Garcia-Herrero
2022	J	`jnl`	Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2021	J	`jnl`	Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
2021	J	`jnl`	Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2013	J	`jnl`	An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. IEEE Trans. Circuits Syst. II Express Briefs Pedro Reviriego, Oscar Ruano, Mark F. Flanagan, Salvatore Pontarelli, Juan Antonio Maestro
2012	J	`jnl`	Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. IEEE Trans. Circuits Syst. II Express Briefs Pedro Reviriego, Oscar Ruano, Juan Antonio Maestro
2011	J	`jnl`	A fast and efficient technique to apply Selective TMR through optimization. Microelectron. Reliab. Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
2011	C	`conf`	Validation and optimization of TMR protections for circuits in radiation environments. DDECS Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
2009	J	`jnl`	Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. Integr. Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano
2008	J	`jnl`	Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. J. Signal Process. Syst. Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano
2007	C	`conf`	An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego