Osamu Nomura

15 papers B 7C 1Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Techniques for Enhancing Memory Capacity of Reservoir Computing.
CoRR
Atsuki Yokota, Ichiro Kawashima, Yohei Saito, Hakaru Tamukoh, Osamu Nomura, Takashi Morie
2024 B conf
A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information.
IJCNN
Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie
2024 B conf
CMOS digital-analog mixed signal VLSI implementation of a hippocampus-inspired model.
IJCNN
Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie
2024 C conf
Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers.
ISCAS
Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
2024 B conf
Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory.
IJCNN
Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie
2023 B conf
Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors.
IJCNN
Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie
2023 B conf
FPGA Implementation of a Chaotic Boltzmann Machine Annealer.
IJCNN
Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh
2022 J jnl
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.
IEEE Trans. Ind. Informatics
Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh
2022 J jnl
Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks.
IEEE Trans. Circuits Syst. II Express Briefs
Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie
2007 — conf
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach.
ICONIP (1)
Osamu Nomura, Takashi Morie
2006 J jnl
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture.
IEICE Trans. Electron.
Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2005 — conf
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations.
ICNC (3)
Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
2004 B conf
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition.
KES
Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
2004 J jnl
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture.
J. Intell. Fuzzy Syst.
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
2003 B conf
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.
KES
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata