Ondrej Novák - RankMe

52 papers A 2B 1C 27Misc 2Journal 9Unranked 11

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	Deterministic Search Strategy of Compression Codes. DSD Ondrej Novák
2023	J	`jnl`	Nonlinear compression block codes: Exact and random search strategy. Microprocess. Microsystems Ondrej Novák
2022	C	`conf`	Nonlinear Compression Block Codes Search Strategy. DSD Ondrej Novák
2021	C	`conf`	Search Strategy of Large Nonlinear Block Codes. DSD Ondrej Novák
2020	J	`jnl`	Decompressors using nonlinear codes. Microprocess. Microsystems Ondrej Novák, Martin Rozkovec, Jan Plíva
2019	C	`conf`	Combinational Decompressors with Nonlinear Codes. DSD Ondrej Novák, Martin Rozkovec, Jan Plíva
2019	A	`conf`	International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019	C	`conf`	Nonlinear Compression Codes Used In IC Testing. DDECS Ondrej Novák
2019	—	`conf`	Portable Bluetooth Microsystem for Electrochemically Modulated Nitric Oxide-Releasing Catheters. BioCAS Ondrej Novák, Kamila K. Konopinska, Mark E. Meyerhoff, Richard B. Brown
2018	J	`jnl`	Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). Microelectron. Reliab. Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz
2018	C	`conf`	Test Compression Using Extended Nonlinear Binary Codes. IOLTS Ondrej Novák
2018	J	`jnl`	Test response compaction method with improved detection and diagnostic abilities. Microelectron. Reliab. Ondrej Novák, Zdenek Plíva
2017	C	`ed.`	20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2017, Dresden, Germany, April 19-21, 2017 DDECS Manfred Dietrich, Ondrej Novák
2017	B	`conf`	Extended binary nonlinear codes and their application in testing and compression. ETS Ondrej Novák
2017	C	`conf`	Logic testing with test-per-clock pattern loading and improved diagnostic abilities. DDECS Ondrej Novák, Zdenek Plíva
2017	J	`jnl`	Sequential Test Decompressors with Fast Tester Bits Wide-Spreading. J. Circuits Syst. Comput. Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2016	C	`conf`	An empirical model of UWB large-scale signal fading in neocortical research. ISCAS Ondrej Novák, Richard B. Brown
2016	C	`conf`	Sequential test decompressors with fast variable wide spreading. DDECS Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2016	C	`conf`	Test Decompressor Effectivity Improvement. DSD Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2015	J	`jnl`	Formation and disruption of tonotopy in a large-scale model of the auditory cortex. J. Comput. Neurosci. Markéta Tomková, Jakub Tomek, Ondrej Novák, Ondrej Zelenka, Josef Syka, Cyril Brom
2015	C	`conf`	LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs. DDECS Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2015	—	`conf`	Test compression for circuits with multiple scan chains. LATS Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2014	—	`conf`	A highly flexible reconfigurable system on a Xilinx FPGA. ReConFig Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák
2014	C	`conf`	Test-data compression with low number of channels and short test time. DDECS Ondrej Novák, Jiri Jenícek, Martin Rozkovec
2013	C	`conf`	Relocation of reconfigurable modules on Xilinx FPGA. DDECS Tomas Drahonovsky, Martin Rozkovec, Ondrej Novák
2013	C	`conf`	Test pattern decompression in parallel scan chain architecture. DDECS Martin Chloupek, Jiri Jenícek, Ondrej Novák, Martin Rozkovec
2012	C	`conf`	An evaluation of the application dependent FPGA test method. DDECS Martin Rozkovec, Jiri Jenícek, Ondrej Novák
2012	C	`conf`	On test time reduction using pattern overlapping, broadcasting and on-chip decompression. DDECS Martin Chloupek, Ondrej Novák, Jiri Jenícek
2011	—	`conf`	Advanced scan chain configuration method for broadcast decompressor architecture. EWDTS Jiri Jenícek, Ondrej Novák, Martin Chloupek
2011	—	`conf`	Scan chain configuration method for broadcast decompressor architecture. LATW Martin Chloupek, Ondrej Novák
2011	C	`conf`	Test vector overlapping based compression tool for narrow test access mechanism. DDECS Jiri Jenícek, Martin Rozkovec, Ondrej Novák
2010	C	`conf`	Application Dependent FPGA Testing Method. DSD Martin Rozkovec, Jiri Jenícek, Ondrej Novák
2010	C	`conf`	Application dependent FPGA testing method using compressed deterministic test vectors. IOLTS Martin Rozkovec, Jiri Jenícek, Ondrej Novák
2010	—	`conf`	COMPAS - Advanced test compressor. EWDTS Jiri Jenícek, Ondrej Novák
2010	C	`conf`	Reconfigurable Fault-Tolerant System Sychronization. DSD Jan Balach, Ondrej Novák
2009	C	`conf`	Structural test of programmed FPGA circuits. DDECS Martin Rozkovec, Ondrej Novák
2007	—	`conf`	A Novel Emulation Technique that Preserves Circuit Structure and Timing. SoC Leos Kafka, Martin Danek, Ondrej Novák
2007	C	`conf`	Test Pattern Compression Based on Pattern Overlapping. DDECS Jiri Jenícek, Ondrej Novák
2006	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
2006	C	`conf`	FPGA-based Fault Simulator. DDECS Leos Kafka, Ondrej Novák
2006	C	`conf`	HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. DDECS Martin Stáva, Ondrej Novák
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2006	—	`conf`	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. DFT Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský
2006	C	`conf`	Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. DSD Martin Stáva, Ondrej Novák
2005	Misc	`conf`	COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits. EDCC Ondrej Novák, Jirí Zahrádka, Zdenek Plíva
2004	J	`jnl`	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. J. Electron. Test. Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa
2003	A	`conf`	Comparison of Test Pattern Decompression Techniques. DATE Ondrej Novák
2001	—	`conf`	Test Pattern Decompression Using a Scan Chain. DFT Ondrej Novák, Jiri Nosek
2001	—	`conf`	Test-per-Clock Testing of the Circuits with Scan. IOLTW Ondrej Novák, Jiri Nosek
2000	—	`conf`	On Using Deterministic Test Sets in BIST. IOLTW Ondrej Novák, Jiri Nosek
1999	Misc	`conf`	Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata. EDCC Ondrej Novák
1988	J	`jnl`	Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. IEEE Trans. Computers Petr Golan, Ondrej Novák, Jan Hlavicka