Omid Hashemipour

38 papers C 1Journal 34Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Novel Rail-to-Rail Input Swing Threshold-Inverter Multi-Bit Quantizer Using Interpolation Technique for Sampled-Data Circuits.
J. Circuits Syst. Comput.
Amir Hossein Miremadi, Omid Hashemipour
2021 J jnl
Intersegment mismatch mitigation with multidimensional dynamic element matching digital to analog converters.
Int. J. Circuit Theory Appl.
Bardia Babaei, Omid Hashemipour
2021 J jnl
Mismatch error shaping of DAC unit elements in multibit ∆Σ modulators using a novel unified ADC/DAC.
Turkish J. Electr. Eng. Comput. Sci.
Leila Sharifi, Omid Hashemipour
2019 J jnl
A charge sharing-based switching scheme for SAR ADCs.
Int. J. Circuit Theory Appl.
Meysam Akbari, Omid Hashemipour, Masoud Nazari, Farshad Moradi
2019 J jnl
An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure.
J. Circuits Syst. Comput.
Mehdi Bandali, Alireza Hassanzadeh, Masoume Ghashghaie, Omid Hashemipour
2019 — conf
Energy-Efficient and Area-Efficient Switching Schemes for SAR ADCs.
MWSCAS
Meysam Akbari, Masoud Nazari, Omid Hashemipour, Kye-Shin Lee
2018 J jnl
A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method.
J. Circuits Syst. Comput.
Meysam Akbari, Omid Hashemipour
2018 C conf
A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths.
ISCAS
Meysam Akbari, Omid Hashemipour, Farshad Moradi
2018 J jnl
A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates.
Integr.
Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi
2018 J jnl
An energy-efficient DAC switching algorithm based on charge recycling method for SAR ADCs.
Microelectron. J.
Meysam Akbari, Omid Hashemipour, Fabian Khateb, Farshad Moradi
2018 J jnl
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion.
IEEE Trans. Very Large Scale Integr. Syst.
Meysam Akbari, Omid Hashemipour, Farshad Moradi
2018 J jnl
Two-Dimensional Structure Compatible with DEM Methods Utilizing in DACs.
J. Circuits Syst. Comput.
Mehdi Bandali, Omid Hashemipour
2017 J jnl
A 63-dB gain OTA operating in subthreshold with 20-nW power consumption.
Int. J. Circuit Theory Appl.
Meysam Akbari, Omid Hashemipour
2017 J jnl
Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta-Sigma Modulator.
Circuits Syst. Signal Process.
Meysam Akbari, Omid Hashemipour, Farshad Moradi
2017 J jnl
Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator.
J. Low Power Electron.
Reza Chavoshisani, Omid Hashemipour
2016 J jnl
Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits.
J. Circuits Syst. Comput.
Meysam Akbari, Omid Hashemipour
2015 J jnl
Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic.
J. Circuits Syst. Comput.
Masoud Nazari, Leila Sharifi, Meysam Akbari, Omid Hashemipour
2015 J jnl
High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation.
J. Circuits Syst. Comput.
Meysam Akbari, Omid Hashemipour
2015 J jnl
New dynamic ternary minimum and maximum circuits with reduced switching activity and without any additional voltage sources.
Int. J. High Perform. Syst. Archit.
Shirin Rezaie, Reza Faghih Mirzaee, Keivan Navi, Omid Hashemipour
2014 J jnl
A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR Filters.
CoRR
Fazel Sharifi, Saba Amanollahi, Mohammad Amin Taherkhani, Omid Hashemipour
2013 J jnl
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits.
IET Comput. Digit. Tech.
Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Akbar Doostaregan, Keivan Navi, Omid Hashemipour
2013 J jnl
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors.
Int. J. High Perform. Syst. Archit.
Shima Mehrabi, Reza Faghih Mirzaee, Sharareh Zamanzadeh, Keivan Navi, Omid Hashemipour
2013 J jnl
Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic.
Microelectron. J.
Reza Faghih Mirzaee, Tooraj Nikoubin, Keivan Navi, Omid Hashemipour
2013 — conf
Dramatically Low-Transistor-Count High-Speed Ternary Adders.
ISMVL
Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Mojtaba Maleknejad, Keivan Navi, Omid Hashemipour
2012 J jnl
A low-variation on-resistance CMOS sampling switch for high-speed high-performance applications.
IEICE Electron. Express
Mohammad Reza Asgari, Omid Hashemipour
2012 J jnl
Design and Evaluation of CNFET-Based Quaternary Circuits.
Circuits Syst. Signal Process.
Mohammad Hossein Moaiyeri, Keivan Navi, Omid Hashemipour
2012 J jnl
High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology.
Circuits Syst. Signal Process.
Mohammad Hossein Moaiyeri, Reza Chavoshisani, Ali Jalali, Keivan Navi, Omid Hashemipour
2011 J jnl
A New Switched opamp Approach for Improving the Operation of Auto-Reset Switched-capacitor Filters.
J. Circuits Syst. Comput.
Mohammad Rashtian, Omid Hashemipour, Keivan Navi, Ali Jalali
2011 J jnl
A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders.
Fuzzy Sets Syst.
Keivan Navi, Akbar Doostaregan, Mohammad Hossein Moaiyeri, Omid Hashemipour
2011 J jnl
A high-speed current conveyor based current comparator.
Microelectron. J.
Reza Chavoshisani, Omid Hashemipour
2011 — conf
A reliable full-swing low-distortion CMOS bootstrapped sampling switch.
ICECS
Mohammad Reza Asgari, Seyyed Hossein Pishgar Komleh, Omid Hashemipour
2011 J jnl
Body effect compensation of analog switches using variable voltage function.
IEICE Electron. Express
Mohammad Reza Asgari, Omid Hashemipour
2010 J jnl
A simple time domain approach to noise analysis of switched capacitor circuits.
IEICE Electron. Express
Mohammad Rashtian, Omid Hashemipour, Ali Mohammad Afshin Hemmatyar
2009 J jnl
An energy efficient full adder cell for low voltage.
IEICE Electron. Express
Keivan Navi, Mehrdad Maeen, Omid Hashemipour
2009 J jnl
Two new low-power Full Adders based on majority-not gates.
Microelectron. J.
Keivan Navi, Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, Omid Hashemipour, Babak Mazloom Nezhad
2008 J jnl
A low voltage bootstrapped switch based on zero DC offset input voltage.
IEICE Electron. Express
Alihosein Sepahvand, Omid Hashemipour
2008 J jnl
An efficient architecture for designing reverse converters based on a general three-moduli set.
J. Syst. Archit.
Amir Sabbagh Molahosseini, Keivan Navi, Omid Hashemipour, Ali Jalali
2008 J jnl
Ultra high speed Full Adders.
IEICE Electron. Express
Keivan Navi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Babak Mazloom Nezhad, Omid Hashemipour, K. Shams