Omer Khan

107 papers A* 6A 13B 8C 13Misc 1Journal 44Unranked 22
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks.
IEEE Comput. Archit. Lett.
Omer Khan
2025 A conf
Graph Input-Aware Matrix Multiplication for Pruned Graph Neural Network Acceleration.
IPDPS
Hanan Khan, Deniz Gurevin, Omer Khan
2025 A conf
OPMOS: Ordered Parallel Algorithm for Multi-Objective Shortest-Paths.
ICS
Leo Gold, Adam Bienkowski, David Sidoti, Krishna R. Pattipati, Omer Khan
2025 J jnl
Secure Remote Attestation With Strong Key Insulation Guarantees.
IEEE Trans. Computers
Deniz Gurevin, Chenglu Jin, Phuong Ha Nguyen, Omer Khan, Marten van Dijk
2024 J jnl
Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency.
IEEE Comput. Archit. Lett.
Deniz Gurevin, Caiwen Ding, Omer Khan
2024 — conf
Masked Memory Primitive for Key Insulated Schemes.
HOST
Zachary DiMeglio, Jenna Bustami, Deniz Gurevin, Chenglu Jin, Marten van Dijk, Omer Khan
2024 — conf
MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training.
ASPLOS (2)
Hongwu Peng, Xi Xie, Kaustubh Shivdikar, Md Amit Hasan, Jiahui Zhao, Shaoyi Huang, Omer Khan, David R. Kaeli, Caiwen Ding
2024 J jnl
OPMOS: Ordered Parallel Multi-Objective Shortest-Path.
CoRR
Leo Gold, Adam Bienkowski, David Sidoti, Krishna R. Pattipati, Omer Khan
2024 A* conf
PruneGNN: Algorithm-Architecture Pruning Framework for Graph Neural Network Acceleration.
HPCA
Deniz Gurevin, Mohsin Shan, Shaoyi Huang, Md Amit Hasan, Caiwen Ding, Omer Khan
2024 — conf
SSE: Security Service Engines to Scale Enclave Parallelism for System Interactive Applications.
SEED
Jared Nye, Usman Ali, Omer Khan
2023 J jnl
ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes.
ACM Trans. Archit. Code Optim.
Abdul Rasheed Sahni, Hamza Omar, Usman Ali, Omer Khan
2023 A conf
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks.
ICCAD
Xi Xie, Hongwu Peng, Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding
2023 J jnl
Accel-GCN: High-Performance GPU Accelerator Design for Graph Convolution Networks.
CoRR
Xi Xie, Hongwu Peng, Amit Hasan, Shaoyi Huang, Jiahui Zhao, Haowen Fang, Wei Zhang, Tong Geng, Omer Khan, Caiwen Ding
2023 J jnl
Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware.
ACM J. Emerg. Technol. Comput. Syst.
Usman Ali, Sheikh Abdul Rasheed Sahni, Omer Khan
2023 J jnl
Hardware Root-of-Trust implementations in Trusted Execution Environments.
IACR Cryptol. ePrint Arch.
Usman Ali, Hamza Omar, Chujiao Ma, Vaibhav Garg, Omer Khan
2023 J jnl
MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training.
CoRR
Hongwu Peng, Xi Xie, Kaustubh Shivdikar, Md Amit Hasan, Jiahui Zhao, Shaoyi Huang, Omer Khan, David R. Kaeli, Caiwen Ding
2023 B conf
MergePath-SpMM: Parallel Sparse Matrix-Matrix Algorithm for Graph Neural Network Acceleration.
ISPASS
Mohsin Shan, Deniz Gurevin, Jared Nye, Caiwen Ding, Omer Khan
2022 J jnl
A performance predictor for implementation selection of parallelized static and temporal graph algorithms.
Concurr. Comput. Pract. Exp.
Akif Rehman, Masab Ahmad, Omer Khan
2022 — conf
Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware.
ISQED
Usman Ali, Salman Abdul Khaliq, Omer Khan
2022 C conf
CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM.
ICCD
YiXuan Luo, Payman Behnam, Kiran Thorat, Zhuo Liu, Hongwu Peng, Shaoyi Huang, Shu Zhou, Omer Khan, Alexey Tumanov, Caiwen Ding, Tong Geng
2022 A* conf
HD-CPS: Hardware-assisted Drift-aware Concurrent Priority Scheduler for Shared Memory Multicores.
HPCA
Mohsin Shan, Omer Khan
2022 C conf
MultiCon: An Efficient Timing-based Side Channel Attack on Shared Memory Multicores.
ICCD
Usman Ali, Omer Khan
2022 C conf
On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond.
ICCD
Zhirui Hu, Jinyang Li, Zhenyu Pan, Shanglin Zhou, Lei Yang, Caiwen Ding, Omer Khan, Tong Geng, Weiwen Jiang
2022 — conf
Protecting On-Chip Data Access Against Timing-Based Side-Channel Attacks on Multicores.
SEED
Usman Ali, Abdul Rasheed Sahni, Omer Khan
2022 J jnl
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors.
IEEE Comput. Archit. Lett.
Jared Nye, Omer Khan
2022 J jnl
Secure Remote Attestation with Strong Key Insulation Guarantees.
CoRR
Deniz Gurevin, Chenglu Jin, Phuong Ha Nguyen, Omer Khan, Marten van Dijk
2022 C conf
Towards Real-Time Temporal Graph Learning.
ICCD
Deniz Gurevin, Mohsin Shan, Tong Geng, Weiwen Jiang, Caiwen Ding, Omer Khan
2022 J jnl
Towards Real-Time Temporal Graph Learning.
CoRR
Deniz Gurevin, Mohsin Shan, Tong Geng, Weiwen Jiang, Caiwen Ding, Omer Khan
2022 C conf
Towards Sparsification of Graph Neural Networks.
ICCD
Hongwu Peng, Deniz Gurevin, Shaoyi Huang, Tong Geng, Weiwen Jiang, Omer Khan, Caiwen Ding
2022 J jnl
Towards Sparsification of Graph Neural Networks.
CoRR
Hongwu Peng, Deniz Gurevin, Shaoyi Huang, Tong Geng, Weiwen Jiang, Omer Khan, Caiwen Ding
2021 J jnl
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores.
IEEE Comput. Archit. Lett.
Mohsin Shan, Omer Khan
2021 — conf
An Efficient Algorithm for the Construction of Dynamically Updating Trajectory Networks.
HPEC
Deniz Gurevin, Chris J. Michael, Omer Khan
2021 J jnl
Autonomous Secure Remote Attestation even when all Used and to be Used Digital Keys Leak.
IACR Cryptol. ePrint Arch.
Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen
2021 J jnl
Bilinear Map Based One-Time Signature Scheme with Secret Key Exposure.
IACR Cryptol. ePrint Arch.
Marten van Dijk, Deniz Gurevin, Chenglu Jin, Omer Khan, Phuong Ha Nguyen
2021 — conf
ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor.
HOST
Usman Ali, Omer Khan
2021 — conf
Message from the General Chairs.
IISWC
Omer Khan, Ravi Soundararajan
2021 J jnl
PRISM: Strong Hardware Isolation-based Soft-Error Resilient Multicore Architecture with High Performance and Availability at Low Hardware Overheads.
ACM Trans. Archit. Code Optim.
Hamza Omar, Omer Khan
2021 — conf
Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors.
SEED
Brandon D'Agostino, Omer Khan
2021 — conf
Timing-based side-channel attack and mitigation on PCIe connected distributed embedded systems.
HPEC
Salman Abdul Khaliq, Usman Ali, Omer Khan
2020 A conf
Accelerating relax-ordered task-parallel workloads using multi-level dependency checking.
ICS
Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan
2020 — conf
Exploring accelerator and parallel graph algorithmic choices for temporal graphs.
PMAM@PPoPP
Akif Rehman, Masab Ahmad, Omer Khan
2020 A* conf
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications.
HPCA
Hamza Omar, Omer Khan
2020 J jnl
In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores.
IEEE Micro
Masab Ahmad, Halit Dogan, José A. Joao, Omer Khan
2020 J jnl
OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks.
IEEE Trans. Computers
Hamza Omar, Brandon D'Agostino, Omer Khan
2019 J jnl
Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale.
ACM Trans. Archit. Code Optim.
Halit Dogan, Masab Ahmad, Brian Kahne, Omer Khan
2019 J jnl
Advancing the State-of-the-Art in Hardware Trojans Detection.
IEEE Trans. Dependable Secur. Comput.
Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk
2019 J jnl
Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design.
IEEE Trans. Emerg. Top. Comput.
Ozgur Sinanoglu, Omer Khan
2019 B conf
HeteroMap: A Runtime Performance Predictor for Efficient Processing of Graph Analytics on Heterogeneous Multi-Accelerators.
ISPASS
Masab Ahmad, Halit Dogan, Christopher J. Michael, Omer Khan
2019 J jnl
IRONHIDE: A Secure Multicore Architecture that Leverages Hardware Isolation Against Microarchitecture State Attacks.
CoRR
Hamza Omar, Omer Khan
2019 B conf
POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms.
PACT
Masab Ahmad, Mohsin Shan, Akif Rehman, Omer Khan
2018 C conf
Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72.
ICCD
Halit Dogan, Masab Ahmad, José A. Joao, Omer Khan
2018 C conf
Breaking the Oblivious-RAM Bandwidth Wall.
ICCD
Hamza Omar, Syed Kamran Haider, Ling Ren, Marten van Dijk, Omer Khan
2018 J jnl
Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency.
ACM Trans. Embed. Comput. Syst.
Hamza Omar, Qingchuan Shi, Masab Ahmad, Halit Dogan, Omer Khan
2018 J jnl
Guest Editorial: Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology.
IEEE Trans. Emerg. Top. Comput.
Maria K. Michael, Salvatore Pontarelli, Omer Khan
2018 J jnl
Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications.
IEEE Comput. Archit. Lett.
Hamza Omar, Halit Dogan, Brian Kahne, Omer Khan
2018 A conf
Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications.
IPDPS
Masab Ahmad, Halit Dogan, Fabio Checconi, Xinyu Que, Daniele Buono, Omer Khan
2017 A conf
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.
IPDPS
Halit Dogan, Farrukh Hijaz, Masab Ahmad, Brian Kahne, Peter Wilson, Omer Khan
2017 J jnl
Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs.
IEEE Micro
Masab Ahmad, Christopher J. Michael, Omer Khan
2017 J jnl
Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads.
CoRR
Qingchuan Shi, Hamza Omar, Omer Khan
2017 C conf
GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph Algorithms.
ICCD
Hamza Omar, Masab Ahmad, Omer Khan
2016 Misc conf
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores.
VLSID
Sandip Kundu, Omer Khan
2016 — conf
Foreword.
DFT
Omer Khan, Maria K. Michael, Antonio Miele, Qiaoyan Yu
2016 — conf
GPU concurrency choices in graph analytics.
IISWC
Masab Ahmad, Omer Khan
2016 J jnl
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.
ACM Trans. Archit. Code Optim.
Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan
2016 J jnl
Locality-aware data replication in the last-level cache for large scale multicores.
J. Supercomput.
Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan
2015 J jnl
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads.
IEEE Comput. Archit. Lett.
Qingchuan Shi, Henry Hoffmann, Omer Khan
2015 — conf
CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.
IISWC
Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan
2015 — conf
Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication.
NAS
Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan
2015 — conf
Efficient parallelization of path planning workload on single-chip shared-memory multicores.
HPEC
Masab Ahmad, Kartik Lakshminarasimhan, Omer Khan
2015 — conf
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads.
HASP@ISCA
Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk, Omer Khan
2015 J jnl
M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors.
IACR Cryptol. ePrint Arch.
Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk
2015 C conf
M-MAP: Multi-factor memory authentication for secure embedded processors.
ICCD
Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk
2015 B conf
OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.
PACT
George Kurian, Qingchuan Shi, Srinivas Devadas, Omer Khan
2015 J jnl
The Execution Migration Machine: Directoryless Shared-Memory Architecture.
Computer
Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas
2014 J jnl
HaTCh: Hardware Trojan Catcher.
IACR Cryptol. ePrint Arch.
Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk
2014 A* conf
Locality-aware data replication in the Last-Level Cache.
HPCA
George Kurian, Srinivas Devadas, Omer Khan
2014 J jnl
NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages.
ACM Trans. Archit. Code Optim.
Farrukh Hijaz, Omer Khan
2014 A* conf
Suppressing the Oblivious RAM timing channel while making information leakage and program efficiency trade-offs.
HPCA
Christopher W. Fletcher, Ling Ren, Xiangyao Yu, Marten van Dijk, Omer Khan, Srinivas Devadas
2014 J jnl
Thread Migration Prediction for Distributed Shared Caches.
IEEE Comput. Archit. Lett.
Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas
2013 C conf
A framework to accelerate sequential programs on homogeneous multicores.
VLSI-SoC
Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas
2013 C conf
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages.
ICCD
Farrukh Hijaz, Qingchuan Shi, Omer Khan
2013 A conf
MARTHA: architecture for control and emulation of power electronics and smart grid systems.
DATE
Michel A. Kinsy, Ivan Celanovic, Omer Khan, Srinivas Devadas
2013 A* conf
The locality-aware adaptive cache coherence protocol.
ISCA
George Kurian, Omer Khan, Srinivas Devadas
2013 J jnl
Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.
Computer
Qingchuan Shi, Omer Khan
2013 C conf
Towards efficient dynamic data placement in NoC-based multicores.
ICCD
Qingchuan Shi, Farrukh Hijaz, Omer Khan
2012 B conf
A low-overhead dynamic optimization framework for multicores.
PACT
Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas
2012 J jnl
Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime.
IET Circuits Devices Syst.
Omer Khan, Sandip Kundu
2012 J jnl
HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pengju Ren, Mieszko Lis, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Nanning Zheng, Srinivas Devadas
2012 — conf
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores.
MICRO Workshops
Farrukh Hijaz, Qingchuan Shi, Omer Khan
2011 C conf
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores.
ICCD
Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas
2011 B conf
Brief announcement: distributed shared memory based on computation migration.
SPAA
Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Christopher W. Fletcher, Michel A. Kinsy, Ilia A. Lebedev, Omer Khan, Srinivas Devadas
2011 J jnl
DCC: A Dependable Cache Coherence Multicore Architecture.
IEEE Comput. Archit. Lett.
Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas
2011 — conf
Deadlock-free fine-grained thread migration.
NOCS
Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas
2011 J jnl
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors.
IEEE Trans. Dependable Secur. Comput.
Omer Khan, Sandip Kundu
2011 J jnl
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors.
Trans. High Perform. Embed. Archit. Compil.
Omer Khan, Sandip Kundu
2011 B conf
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores.
PACT
Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan
2011 B conf
Scalable, accurate multicore simulation in the 1000-core era.
ISPASS
Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas
2011 A conf
Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.
RTSS
Michel A. Kinsy, Omer Khan, Ivan Celanovic, Dusan Majstorovic, Nikola L. Celanovic, Srinivas Devadas
2010 — conf
A model to exploit power-performance efficiency in superscalar processors via structure resizing.
ACM Great Lakes Symposium on VLSI
Omer Khan, Sandip Kundu
2010 — conf
A self-adaptive scheduler for asymmetric multi-cores.
ACM Great Lakes Symposium on VLSI
Omer Khan, Sandip Kundu
2010 A conf
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor.
ITC
Rance Rodrigues, Sandip Kundu, Omer Khan
2010 J jnl
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.
IEEE Trans. Computers
Omer Khan, Sandip Kundu
2009 A conf
A self-adaptive system architecture to address transistor aging.
DATE
Omer Khan, Sandip Kundu
2009 A conf
Hardware/software co-design architecture for thermal management of chip multiprocessors.
DATE
Omer Khan, Sandip Kundu
2009 A conf
Improving yield and reliability of chip multiprocessors.
DATE
Abhisek Pan, Omer Khan, Sandip Kundu
2009 — conf
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines.
HiPEAC
Omer Khan, Sandip Kundu
2008 A conf
A framework for predictive dynamic temperature management of microprocessor systems.
ICCAD
Omer Khan, Sandip Kundu