Olivier Muller

33 papers A 3B 4C 8Misc 1Journal 14Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	ODySSeI: An Open-Source End-to-End Framework for Automated Detection, Segmentation, and Severity Estimation of Lesions in Invasive Coronary Angiography Images. CoRR Anand Choudhary, Xiaowu Sun, Thabo Mahendiran, Ortal Yona Senouf, Denise Auberson, Bernard De Bruyne, Stéphane Fournier, Olivier Muller, Emmanuel Abbe, Pascal Frossard, Dorina Thanou
2026	J	`jnl`	Pipeline Automation Framework for Reusable High-throughput Network Applications on FPGA. CoRR Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Frédéric Pétrot
2025	J	`jnl`	CM-UNet: A Self-Supervised Learning-Based Model for Coronary Artery Segmentation in X-Ray Angiography. CoRR Camille Challier, Xiaowu Sun, Thabo Mahendiran, Ortal Yona Senouf, Bernard De Bruyne, Denise Auberson, Olivier Muller, Stéphane Fournier, Pascal Frossard, Emmanuel Abbe, Dorina Thanou
2025	J	`jnl`	Physics-informed self-supervised learning for predictive modeling of coronary artery digital twins. CoRR Xiaowu Sun, Thabo Mahendiran, Ortal Yona Senouf, Denise Auberson, Bernard De Bruyne, Stéphane Fournier, Olivier Muller, Pascal Frossard, Emmanuel Abbe, Dorina Thanou
2024	—	`conf`	Graph Neural Network based Future Clinical Events Prediction from Invasive Coronary Angiography. ISBI Xiaowu Sun, Theofilos Belmpas, Ortal Yona Senouf, Emmanuel Abbe, Pascal Frossard, Bernard De Bruyne, Olivier Muller, Stéphane Fournier, Thabo Mahendiran, Dorina Thanou
2023	J	`jnl`	A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. CoRR Bruno Ferres, Olivier Muller, Frédéric Rousseau
2023	J	`jnl`	A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. ACM Trans. Design Autom. Electr. Syst. Bruno Ferres, Olivier Muller, Frédéric Rousseau
2023	B	`conf`	Can Knowledge Transfer Techniques Compensate for the Limited Myocardial Infarction Data by Leveraging Hæmodynamics? An in silico Study. AIME Riccardo Tenderini, Federico Betti, Ortal Yona Senouf, Olivier Muller, Simone Deparis, Annalisa Buffa, Emmanuel Abbe
2022	J	`jnl`	Toward Agile Hardware Designs With Chisel: A Network Use Case. IEEE Des. Test Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot
2021	J	`jnl`	Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. ACM Trans. Reconfigurable Technol. Syst. Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller
2021	C	`conf`	Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. RSP Bruno Ferres, Olivier Muller, Frédéric Rousseau
2020	C	`conf`	(System)Verilog to Chisel Translation for Faster Hardware Design. RSP Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot
2020	—	`conf`	Chisel Usecase: Designing General Matrix Multiply for FPGA. ARC Bruno Ferres, Olivier Muller, Frédéric Rousseau
2019	J	`jnl`	Efficient Decompression of Binary Encoded Balanced Ternary Sequences. IEEE Trans. Very Large Scale Integr. Syst. Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot
2018	—	`conf`	An FPGA target for the StarPU heterogeneous runtime system. ReCoSoC Georgios Christodoulis, François Broquedis, Olivier Muller, Manuel Selva, Frederic Desprez
2018	C	`conf`	Message-Oriented Devices on FPGAs. RSP Thomas Baumela, Olivier Gruber, Olivier Muller, Frédéric Pétrot
2017	C	`conf`	Prototyping dynamic task migration on heterogeneous reconfigurable systems. RSP Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau
2016	B	`conf`	Demonstration of a context-switch method for heterogeneous reconfigurable systems. FPL Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
2016	J	`jnl`	Demonstration of a context-switch method for heterogeneous reconfigurable systems. CoRR Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau
2016	J	`jnl`	Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow. ACM Trans. Reconfigurable Technol. Syst. Alban Bourge, Olivier Muller, Frédéric Rousseau
2016	C	`conf`	HLS-Based Methodology for Fast Iterative Development Applied to Elliptic Curve Arithmetic. DSD Simon Pontie, Alban Bourge, Adrien Prost-Boucle, Paolo Maistri, Olivier Muller, Régis Leveugle, Frédéric Rousseau
2016	C	`conf`	On-board non-regression test of HLS tools targeting FPGA. RSP Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau, Arif Sasongko
2015	A	`conf`	A Novel Method for Enabling FPGA Context-Switch (Abstract Only). FPGA Alban Bourge, Olivier Muller, Frédéric Rousseau
2015	Misc	`conf`	Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. FCCM Alban Bourge, Olivier Muller, Frédéric Rousseau
2014	J	`jnl`	Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints. J. Syst. Archit. Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau
2013	C	`conf`	A Fast and Autonomous HLS Methodology for Hardware Accelerator Generation under Resource Constraints. DSD Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau
2012	B	`conf`	HCM: An abstraction layer for seamless programming of DPR FPGA. FPL Yan Xu, Olivier Muller, Pierre-Henri Horrein, Frédéric Pétrot
2010	J	`jnl`	Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. Olivier Muller, Amer Baghdadi, Michel Jézéquel
2009	J	`jnl`	From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. Olivier Muller, Amer Baghdadi, Michel Jézéquel
2008	C	`conf`	From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping Olivier Muller, Amer Baghdadi, Michel Jézéquel
2007	A	`conf`	Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
2006	A	`conf`	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE Olivier Muller, Amer Baghdadi, Michel Jézéquel
2006	B	`conf`	On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM Olivier Muller, Amer Baghdadi, Michel Jézéquel