Olivier Billoint

35 papers A 3C 4Journal 3Unranked 25

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Dual-Mode 16kb Memory: Transforming a Ferroelectric Capacitor Bitcell into Resistive Filamentary Memory. IMW Tarcisius Januel, Olivier Billoint, Laurent Grenouillet, S. Martin, Jean-Michel Portal, Elisa Vianello
2025	C	`conf`	Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. DDECS Claire Fenouillet-Béranger, Laurent Fesquet, Rihab Chouk, Gabriel Pares, Baudouin Martineau, Marie Claire Cyrille, Thierry Poiroux, Olivier Billoint, Dominique Noguet
2024	—	`conf`	Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome CBL-induced Bank Size Limitations. IMW Olivier Billoint, Simon Martin, J. Laguerre, L. Hosier, Jean Coignus, Catherine Carabasse, François Andrieu, Laurent Grenouillet
2023	—	`conf`	Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced Nodes. IMW J. Laguerre, Marc Bocquet, Olivier Billoint, Simon Martin, Jean Coignus, Catherine Carabasse, Thomas Magis, T. Dewolf, François Andrieu, Laurent Grenouillet
2021	—	`conf`	16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors. IMW Laurent Grenouillet, Niccolo Castellani, Alain Persico, Valentina Meli, Simon Martin, Olivier Billoint, R. Segaud, Stefania Bernasconi, C. Pellissier, Carine Jahan, Christelle Charpin-Nicolle, P. Dezest, Catherine Carabasse, Paul Besombes, Sebastien Ricavy, N. P. Tran, A. Magalhaes-Lucas, A. Roman, C. Boixaderas, Thomas Magis, Messaoud Bedjaoui, M. Tessaire, A. Seignard, F. Mazen, S. Landis, Elisa Vianello, Gabriel Molas, Fred Gaillard, Julien Arcamone, Etienne Nowak
2021	—	`conf`	Area and Cost Analysis of the Mixed Signal Circuits in a Novel Monolithic 3D Process. MWSCAS Behnam Samadpoor Rikan, Philipp Häfliger, Gerald Cibrario, Olivier Billoint, Mehdi Mouhdach
2020	A	`conf`	M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC. DATE Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard
2019	—	`conf`	Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations. 3DIC Olivier Billoint, Karim Azizi-Mourier, Gerald Cibrario, Didier Lattard, Mehdi Mouhdach, Sébastien Thuries, Pascal Vivet
2019	J	`jnl`	Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard
2018	—	`conf`	A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit. ICICDT François Andrieu, Perrine Batude, Laurent Brunet, Claire Fenouillet-Béranger, Didier Lattard, Sébastien Thuries, Olivier Billoint, Richard Fournel, Maud Vinet
2018	—	`conf`	Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
2017	J	`jnl`	Cell-on-Buffer: New design approach for high-performance and low-power monolithic 3D integrated circuits. Microelectron. J. Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
2017	C	`conf`	In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
2017	—	`conf`	Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells. ISVLSI Melanie Brocard, Benoît Mathieu, Jean-Philippe Colonna, Cristiano Santos, Claire Fenouillet-Béranger, Cao-Minh Vincent Lu, Gerald Cibrario, Laurent Brunet, Perrine Batude, François Andrieu, Sébastien Thuries, Olivier Billoint
2016	—	`conf`	From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose. 3DIC Gerald Cibrario, Nour Ben Salem, Joris Lacord, Karim Azizi-Mourier, Olivier Rozeau, Etienne Maurin, Olivier Billoint, Sébastien Thuries, Alexandre Valentian
2016	—	`conf`	Impact of intermediate BEOL technology on standard cell performances of 3D VLSI. ESSDERC Melanie Brocard, Guillaume Berhault, Sébastien Thuries, Fabien Clermidy, Perrine Batude, Claire Fenouillet-Béranger, Laurent Brunet, François Andrieu, Fabien Deprat, Joris Lacord, Olivier Rozeau, Gerald Cibrario, Olivier Billoint
2016	—	`conf`	Opportunities brought by sequential 3D CoolCube™ integration. ESSDERC Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Guillaume Berhault, Cristiano Lopes Dos Santos, Gerald Cibrario, Fabien Clermidy, Daniel Gitlin, Olivier Faynot
2016	—	`conf`	Recent advances in 3D VLSI integration. ICICDT Claire Fenouillet-Béranger, Perrine Batude, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, M.-P. Samson, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Gerald Cibrario, Maud Vinet
2016	—	`conf`	Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes. 3DIC Cristiano Santos, Pascal Vivet, Sébastien Thuries, Olivier Billoint, Jean-Philippe Colonna, Perceval Coudrain, Lee Wang
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	A	`conf`	A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool. DATE Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, A. Fustier, Julien Michallet, Olivier Faynot, Ogun Turkyilmaz, Jean-Frédéric Christmann, Sébastien Thuries, Fabien Clermidy
2015	—	`conf`	A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko
2015	—	`conf`	An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits. ISVLSI Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
2015	C	`conf`	Compact interconnect approach for networks of neural cliques using 3D technology. VLSI-SoC Bartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
2015	—	`conf`	From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges. ISPD Olivier Billoint, Hossam Sarhan, Iyad Rayane, Maud Vinet, Perrine Batude, Claire Fenouillet-Béranger, Olivier Rozeau, Gerald Cibrario, Fabien Deprat, Ogun Turkyilmaz, Sébastien Thuries, Fabien Clermidy
2015	—	`conf`	Intermediate BEOL process influence on power and performance for 3DVLSI. 3DIC Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy
2015	—	`conf`	UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. ESSDERC Edith Beigné, Jean-Frédéric Christmann, Alexandre Valentian, Olivier Billoint, Esteve Amat, Dominique Morche
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014	—	`conf`	3D technologies for reconfigurable architectures. ReCoSoC Fabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon
2014	—	`conf`	3DCoB: A new design approach for Monolithic 3D Integrated circuits. ASP-DAC Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy
2014	—	`conf`	A high-level design rule library addressing CMOS and heterogeneous technologies. ICICDT Gerald Cibrario, Marjorie Gary, Fabien Gays, Karim Azizi-Mourier, Olivier Billoint, Ogun Turkyilmaz, Olivier Rozeau
2013	—	`conf`	Distributed clock generator for synchronous SoC using ADPLL network. CICC Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard
2013	C	`conf`	FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? ISCAS Jani Mäkipää, Olivier Billoint
2013	—	`conf`	FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson