Oliver Schrape

47 papers C 11Journal 8Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	ImSTDP: Implicit Timing On-Chip STDP Learning. IEEE Trans. Circuits Syst. I Regul. Pap. Dedong Zhao, Oliver Schrape, Zoran Stamenkovic, Milos Krstic
2025	—	`conf`	Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications. DFT Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic
2024	—	`conf`	Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction. NorCAS Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic
2023	—	`—`	Methodology for standard cell-based design and implementation of reliable and robust hardware systems (Methoden für Standardzellbasiertes Design und Implementierung zuverlässiger und robuster Hardware Systeme) Oliver Schrape
2023	—	`conf`	SET and SEU Hardened Clock Gating Cell. DCIS Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic
2022	J	`jnl`	A design concept for radiation hardened RADFET readout system for space applications. Microprocess. Microsystems Marko S. Andjelkovic, Aleksandar Simevski, Junchao Chen, Oliver Schrape, Zoran Stamenkovic, Milos Krstic, Stefan D. Ilic, Goran S. Ristic, Aleksandar Jaksic, Nikola Vasovic, Russell Duane, Alberto J. Palma, Antonio M. Lallena, Miguel Ángel Carvajal
2022	J	`jnl`	Analysis of Single Event Transient Effects in Standard Delay Cells Based on Decoupling Capacitors. J. Circuits Syst. Comput. Marko S. Andjelkovic, Milos Marjanovic, Bojan Drasko, Cristiano Calligaro, Oliver Schrape, Umberto Gatti, Felipe A. Kuentzer, Stefan D. Ilic, Goran S. Ristic, Milos Krstic
2022	J	`jnl`	Fast Error Propagation Probability Estimates by Answer Set Programming and Approximate Model Counting. IEEE Access Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic
2022	—	`conf`	Ultra High-Speed BP Decoder for Polar Codes achieving 1.4 Tbps in 28 nm CMOS. EuCNC Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, Jesús Gutiérrez, Milos Krstic, Eckhard Grass
2022	—	`conf`	Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS. VTC Spring Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Oliver Schrape, Jesús Gutiérrez, Milos Krstic, Eckhard Grass, Rolf Kraemer
2021	—	`conf`	A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells. DFT Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Junchao Chen, Milos Krstic
2021	J	`jnl`	Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Steffen Zeidler, Alexey Balashov, Milos Krstic
2021	—	`conf`	Machine Learning Approach for Accelerating Simulation-based Fault Injection. NorCAS Li Lu, Junchao Chen, Anselm Breitenreiter, Oliver Schrape, Markus Ulbricht, Milos Krstic
2021	J	`jnl`	Monitoring of Particle Flux and LET Variations with Pulse Stretching Inverters. CoRR Marko S. Andjelkovic, Junchao Chen, Aleksandar Simevski, Oliver Schrape, Milos Krstic, Rolf Kraemer
2021	—	`conf`	Power- and Area-optimized Neural Network IC-Design for Academic Education. ICECS Florian Frankreiter, Anselm Breitenreiter, Oliver Schrape, Milos Krstic
2021	—	`conf`	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. LASCAS Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler, Milos Krstic
2021	—	`conf`	Reliability Analysis in Less than 200 Lines of Code. LASCAS Anselm Breitenreiter, Oliver Schrape, Marko S. Andjelkovic, Milos Krstic
2020	C	`conf`	A Glitch-free Clock Multiplexer for Non-Continuously Running Clocks. DSD Steffen Zeidler, Oliver Schrape, Anselm Breitenreiter, Milos Krstic
2020	—	`conf`	Characterization of Single Event Transient Effects in Standard Delay Cells. ICECS Marko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Milos Krstic, Rolf Kraemer
2020	C	`conf`	Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops. DSD Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic
2020	C	`conf`	Design of Radiation Hardened RADFET Readout System for Space Applications. DSD Marko S. Andjelkovic, Aleksandar Simevski, Junchao Chen, Oliver Schrape, Zoran Stamenkovic, Milos Krstic, Stefan D. Ilic, Luka Spahic, Laza Kostic, Goran S. Ristic, Aleksandar Jaksic, Alberto J. Palma, Antonio M. Lallena, Miguel Ángel Carvajal
2020	C	`conf`	PISA: Power-robust Multiprocessor Design for Space Applications. IOLTS Aleksandar Simevski, Oliver Schrape, Carlos Benito, Milos Krstic, Marko S. Andjelkovic
2020	—	`conf`	R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing Constraints. ISVLSI Christos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic, Oliver Schrape, Anselm Breitenreiter
2020	—	`conf`	Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures. ASYNC Felipe A. Kuentzer, Moisés Herrera, Oliver Schrape, Peter A. Beerel, Milos Krstic
2019	C	`conf`	Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-Flops. DSD Oliver Schrape, Anselm Breitenreiter, Steffen Zeidler, Milos Krstic
2019	C	`conf`	Selective Fault Tolerance by Counting Gates with Controlling Value. IOLTS Anselm Breitenreiter, Stefan Weidling, Oliver Schrape, Steffen Zeidler, Pedro Reviriego, Milos Krstic
2018	—	`conf`	A Radiation Hardened 16 GS/s Arbitrary Waveform Generator IC for a Submillimeter Wave Chirp-Transform Spectrometer. NORCAS P. Ostrovsky, Oliver Schrape, Klaus Tittelbach-Helmrich, Frank Herzel, Gunter Fischer, D. Hellmann, P. Borner, A. Loose, P. Hartogh, Dietmar Kissinger
2018	C	`conf`	D-SET Mitigation Using Common Clock Tree Insertion Techniques for Triple-Clock TMR Flip-Flop. DSD Oliver Schrape, Anselm Breitenreiter, Marko S. Andjelkovic, Milos Krstic
2018	—	`conf`	Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip. DCIS Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi
2018	C	`conf`	Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. DDECS Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic
2018	—	`conf`	Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment. ACM Great Lakes Symposium on VLSI Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi
2018	—	`conf`	Master-Clone Placement with Individual Clock Tree Implementation - a Case on Physical Chip Design. NORCAS Oliver Schrape, Alexey Balashov, Aleksandar Simevski, Carlos Benito, Milos Krstic
2018	—	`conf`	Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates. ICECS Marko S. Andjelkovic, Milan Babic, Yuanqing Li, Oliver Schrape, Milos Krstic, Rolf Kraemer
2017	—	`conf`	A single chip 16 GS/s arbitrary waveform generator in 0.13 μm BiCMOS technology. NORCAS P. Ostrovsky, Klaus Tittelbach-Helmrich, Frank Herzel, Oliver Schrape, Gunter Fischer, Dietmar Kissinger, P. Borner, A. Loose, D. Hellmann, P. Hartogh
2017	C	`conf`	Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. DDECS Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic
2016	J	`jnl`	An Early Stage Design Flow for Switching Noise Attenuation. J. Circuits Syst. Comput. Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
2016	J	`jnl`	Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling. IEEE Trans. Circuits Syst. I Regul. Pap. Xin Fan, Mikkel B. Stegmann, Oliver Schrape, Steffen Zeidler, Isac G. Jensen, Jannich Thorsen, Tobias Bjerregaard, Milos Krstic
2016	C	`conf`	Implementation of DBFN processor for Synthetic Aperture Radar application. DDECS Oliver Schrape, Arkadiusz Koczor, Piotr Penkala, Vladimir Petrovic, Milos Krstic
2015	C	`conf`	A Design Preconditioning Flow for Low-Noise Circuits. DDECS Steffen Zeidler, Xin Fan, Oliver Schrape, Milos Krstic
2014	—	`conf`	Low-power design methodology for CML and ECL circuits. PATMOS Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
2013	—	`conf`	A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface. ICECS Oliver Schrape, Markus Appel, Frank Winkler, Milos Krstic
2013	—	`conf`	GALS Design for Spectral Peak Attenuation of Switching Current. ASYNC Xin Fan, Oliver Schrape, Miroslav Marinkovic, Peter Dahnert, Milos Krstic, Eckhard Grass
2013	—	`conf`	TNODE: A low power sensor node processor for secure wireless networks. ISSoC Goran Panic, Oliver Schrape, Thomas Basmer, Frank Vater, Klaus Tittelbach-Helmrich
2012	—	`conf`	Embedded low power clock generator for sensor nodes. NORCHIP Oliver Schrape, Frank Vater
2011	—	`conf`	Sensor node processor for security applications. ICECS Goran Panic, Thomas Basmer, Oliver Schrape, Steffen Peter, Frank Vater, Klaus Tittelbach-Helmrich
2010	—	`conf`	An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. PATMOS Oliver Schrape, Frank Winkler, Steffen Zeidler, Markus Petri, Eckhard Grass, Ulrich Jagdhold
2009	—	`conf`	HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. MBMV Frank Winkler, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold