Oliver Schliebusch

14 papers A* 2A 4C 2Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2007 — book
Optimized ASIP synthesis from architecture description language models.
Oliver Schliebusch, Heinrich Meyr, Rainer Leupers
2006 — conf
ASIP design and synthesis for non linear filtering in image processing.
DATE Designers' Forum
Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2006 A conf
Automatic ADL-based operand isolation for embedded processors.
DATE
Anupam Chattopadhyay, Benedikt Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2005 — conf
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
ASP-DAC
Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
2005 C conf
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.
ICCD
Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler
2005 C conf
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
IEEE International Workshop on Rapid System Prototyping
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2004 J jnl
A universal technique for fast and flexible instruction-set architecture simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
2004 A conf
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE
Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
2003 A* conf
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
DAC
Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
2003 A conf
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
DATE
Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
2002 A* conf
A universal technique for fast and flexible instruction-set architecture simulation.
DAC
Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
2002 — conf
Architecture Implementation Using the Machine Description Language LISA.
ASP-DAC/VLSI Design
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr
2001 A conf
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.
ICCAD
Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr
2001 J jnl
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr