Oliver Keszöcze

62 papers A* 3A 8B 1C 5Misc 2Journal 25Unranked 16
YearRankTypeTitle / Venue / Authors
2025 — conf
Binarization and Classification of RGB Images.
ISMVL
Tagir Nukenov, Kamila Abdiyeva, Oliver Keszöcze, Shinobu Nagayama, Martin Lukac
2025 J jnl
Reconfigurable Digital FPGA Implementations for Neuromorphic Computing: A Survey on Recent Advances and Future Directions.
IEEE Trans. Emerg. Top. Comput. Intell.
Edris Zaman Farsa, Arash Ahmadi, Oliver Keszöcze
2024 J jnl
Approximate synthesis for LUT count reduction via probabilistic error propagation.
it Inf. Technol.
Thomas Schlögl, Oliver Keszöcze
2024 C conf
DSL-Based SNN Accelerator Design Using Chisel.
DSD
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2024 J jnl
Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms.
IEICE Trans. Inf. Syst.
Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze, Abilmansur Rakhmettulayev, Michitaka Kameyama
2024 C conf
Hardware Generators with Chisel.
DSD
Martin Schoeberl, Hans Jakob Damsgaard, Luca Pezzarossa, Oliver Keszöcze, Erling Rennemo Jellum
2024 A conf
Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes.
GECCO
Matthias Kergaßner, Oliver Keszöcze, Rolf Wanka
2024 J jnl
Markov Chain-based Optimization Time Analysis of Bivalent Ant Colony Optimization for Sorting and LeadingOnes.
CoRR
Matthias Kergaßner, Oliver Keszöcze, Rolf Wanka
2024 A* conf
SAS - A Framework for Symmetry-based Approximate Synthesis.
DAC
Niklas Jungnitz, Oliver Keszöcze
2024 — conf
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation.
ARC
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2023 J jnl
Artificial Intelligence for Molecular Communication.
CoRR
Max Bartunik, Jens Kirchner, Oliver Keszöcze
2023 J jnl
Artificial intelligence for molecular communication.
it Inf. Technol.
Max Bartunik, Jens Kirchner, Oliver Keszöcze
2023 J jnl
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations.
CoRR
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2022 J jnl
Approximate Computing.
it Inf. Technol.
Oliver Keszöcze
2022 J jnl
BDD-Based Error Metric Analysis, Computation and Optimization.
IEEE Access
Oliver Keszöcze
2022 B conf
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
FPL
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022 J jnl
DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks.
CoRR
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022 J jnl
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains.
it Inf. Technol.
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2022 J jnl
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks.
CoRR
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022 J jnl
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022 J jnl
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview.
IEEE Trans. Circuits Syst. II Express Briefs
Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
2022 J jnl
Towards Clause Learning à la Carte through VarMonads.
CoRR
Arved Friedemann, Oliver Keszöcze
2022 — conf
Using Deep Learning to Demodulate Transmissions in Molecular Communication.
ISMICT
Max Bartunik, Oliver Keszöcze, Benjamin Schiller, Jens Kirchner
2021 Misc conf
Aarith: an arbitrary precision number library.
SAC
Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
2021 — conf
Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors.
PKDD/ECML Workshops (1)
Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich
2021 J jnl
Efficient One-pass Synthesis for Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst.
Naser MohammadZadeh, Robert Wille, Oliver Keszöcze
2021 A conf
Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures.
DATE
Oliver Keszöcze, Naser MohammadZadeh, Robert Wille
2021 J jnl
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains.
CoRR
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2020 A conf
A fast BDD Minimization Framework for Approximate Computing.
DATE
Andreas Wendler, Oliver Keszöcze
2020 C conf
Geometric Refactoring of Quantum and Reversible Circuits: Quantum Layout.
DSD
Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze
2020 — conf
One-pass Synthesis for Digital Microfluidic Biochips: A Survey.
ISDCS
Oliver Keszöcze, Robert Wille, Rolf Drechsler
2020 A* conf
Probabilistic Error Propagation through Approximated Boolean Networks.
DAC
Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich
2020 — conf
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems.
ASP-DAC
Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann
2019 C conf
Chatbot-based assertion generation from natural language specifications.
FDL
Oliver Keszöcze, Ian G. Harris
2018 Misc conf
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
VLSID
Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2018 J jnl
On the complexity of design tasks for Digital Microfluidic Biochips.
Microelectron. J.
Oliver Keszöcze, Philipp Niemann, Arved Friedemann, Rolf Drechsler
2018 J jnl
The complexity of error metrics.
Inf. Process. Lett.
Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
2018 — conf
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws.
ISVLSI
Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
2018 — conf
Translating Between the Roots of the Identity in Quantum Computers.
ISMVL
Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken
2017 J jnl
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs.
J. Low Power Electron.
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2017 — conf
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips.
ISVLSI
Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
2017 A conf
Effects of cell shapes on the routability of Digital Microfluidic Biochips.
DATE
Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
2017 — conf
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips.
MBMV
Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
2017 — —
Exact design of digital microfluidic biochips.
Oliver Keszöcze
2017 — conf
Exact routing for micro-electrode-dot-array digital microfluidic biochips.
ASP-DAC
Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2017 — ch.
Exakter Entwurf digitaler mikrofluidischer Biochips.
Ausgezeichnete Informatikdissertationen
Oliver Keszöcze
2017 J jnl
Synthesis of optical circuits using binary decision diagrams.
Integr.
Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
2016 J jnl
Embedding of Large Boolean Functions for Reversible Logic.
ACM J. Emerg. Technol. Comput. Syst.
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2016 J jnl
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.
ACM J. Emerg. Technol. Comput. Syst.
Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
2016 — conf
Generating and checking control logic in the HDL-based design of reversible circuits.
ISED
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2016 C conf
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report.
RC
Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
2016 — conf
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.
ASP-DAC
Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
2016 A conf
Synthesis of approximate coders for on-chip interconnects using reversible logic.
DATE
Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto García Ortiz
2015 A conf
A General and Exact Routing Methodology for Digital Microfluidic Biochips.
ICCAD
Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
2015 — conf
Reverse BDD-based synthesis for splitter-free optical circuits.
ASP-DAC
Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
2015 J jnl
Scalable One-Pass Synthesis for Digital Microfluidic Biochips.
IEEE Des. Test
Robert Wille, Oliver Keszöcze, Rolf Drechsler, Tobias Boehnisch, Alexander Kroker
2014 — conf
A Logic for Cardinality Constraints (Extended Abstract).
MBMV
Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
2014 J jnl
Embedding of Large Boolean Functions for Reversible Logic.
CoRR
Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
2014 A* conf
Exact One-pass Synthesis of Digital Microfluidic Biochips.
DAC
Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
2014 A conf
Exact routing for digital microfluidic biochips with temporary blockages.
ICCAD
Oliver Keszöcze, Robert Wille, Rolf Drechsler
2013 — conf
Task-Driven Software Summarization.
ICSM
Dave W. Binkley, Dawn J. Lawrie, Emily Hill, Janet E. Burge, Ian G. Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas
2011 A conf
Determining the minimal number of lines for large reversible circuits.
DATE
Robert Wille, Oliver Keszöcze, Rolf Drechsler