Olga Casals

37 papers A* 1A 1B 3C 1Journal 13Unranked 16
YearRankTypeTitle / Venue / Authors
2024 conf
IEEE SENSORS
Juan Luis Soler-Fernández, Olga Casals, Cristian Fàbrega, Ángel Diéguez, Joan Daniel Prades, Oscar Alonso
2023 J jnl
Pattern Recognit.
Ismael Benito-Altamirano, David Martínez-Carpena, Olga Casals, Cristian Fàbrega, Andreas Waag, Joan Daniel Prades
2020 J jnl
Sensors
Qomaruddin Qomaruddin, Olga Casals, Andris Sutka, Tony Granz, Andreas Waag, Hutomo Suryo Wasisto, Joan Daniel Prades, Cristian Fàbrega
2019 conf
ISOEN
Olga Casals, Nicolai Markiewicz, Cristian Fàbrega, Isabel Gràcia, Carles Cané, Hutomo Suryo Wasisto, Andreas Waag, Joan Daniel Prades
2019 conf
ISOEN
Christian Driau, Cristian Fàbrega, Ismael Benito-Altamirano, Peter Pfeiffer, Olga Casals, Joan Daniel Prades
2019 conf
ISOEN
Nicolai Markiewicz, Olga Casals, Jiushuai Xu, Muhammad Fahlesa Fatahilah, Angelika Schmidt, Hutomo Suryo Wasisto, Erwin Peiner, Andreas Waag, Joan Daniel Prades
2004 J jnl
Mob. Networks Appl.
Chris Blondia, Olga Casals, Llorenç Cerdà, Nik Van den Wijngaert, Gert Willems
2004 J jnl
Wirel. Networks
Llorenç Cerdà, Fabio Vena, Olga Casals
2003 ch.
QofIS Final Report
Chris Blondia, Nik Van den Wijngaert, Gert Willems, Olga Casals, Llorenç Cerdà, Marcelo Bagnulo, Ignacio Soto
2003 conf
ICC
Olga Casals, Llorenç Cerdà, Gert Willems, Chris Blondia, Nik Van den Wijngaert
2003 book
Michael Smirnov, Ernst W. Biersack, Chris Blondia, Olivier Bonaventure, Olga Casals, Gunnar Karlsson, George Pavlou, Bruno Quoitin, James Roberts, Ioannis Stavrakakis, Burkhard Stiller, Panos Trimintzios, Piet Van Mieghem
2002 conf
Protocols for High-Speed Networks
Chris Blondia, Olga Casals, Peter De Cleyn, Gert Willems
2002 B conf
NETWORKING
Chris Blondia, Olga Casals, Llorenç Cerdà, Gert Willems
2002 A conf
MSWiM
Chris Blondia, Nik Van den Wijngaert, Gert Willems, Olga Casals
2001 J jnl
J. Interconnect. Networks
Benny Van Houdt, Chris Blondia, Olga Casals, Jorge García-Vidal
2000 B conf
NETWORKING
Fernando Cerdán, Olga Casals
2000 J jnl
IEEE/ACM Trans. Netw.
José M. Barceló, Jorge García-Vidal, Olga Casals
1999 B conf
LCN
Benny Van Houdt, Chris Blondia, Olga Casals, Jorge García-Vidal
1999 C conf
WOWMOM
Benny Van Houdt, Chris Blondia, Olga Casals, Jorge García-Vidal, D. Vazquez
1999 conf
Broadband Communications
Llorenç Cerdà, Olga Casals, Benny Van Houdt, Chris Blondia
1998 conf
PICS
Chris Blondia, Olga Casals, Benny Van Houdt
1996 J jnl
Eur. Trans. Telecommun.
Laurent Jaussi, Jose-Maria Barcelo, Stéphane Louis, Olga Casals
1996 J jnl
Telecommun. Syst.
Chris Blondia, Olga Casals
1995 conf
Modelling and Evaluation of ATM Networks
Llorenç Cerdà, Jorge García-Vidal, Olga Casals
1995 conf
Data Communications and their Performance
Jorge García-Vidal, José M. Barceló, Olga Casals
1994 J jnl
Perform. Evaluation
Jorge García-Vidal, Olga Casals
1994 J jnl
Eur. Trans. Telecommun.
John Paul Cosmas, Guido H. Petit, Ralf Lehnert, Chris Blondia, Kimon Kontovassilis, Olga Casals, Thomas Theimer
1994 conf
CAMAD
Chris Blondia, Olga Casals, Jorge García-Vidal, Frans J. M. Panken
1994 J jnl
Eur. Trans. Telecommun.
Tiziana Toniatti, Luigi Verri, Olga Casals, Jorge García-Vidal, Chris Blondia, John D. Angelopoulos, Iakovos S. Venieris
1993 conf
Data Communication Networks and their Performance
Olga Casals, Jorge García-Vidal, Chris Blondia
1993 conf
Modelling and Evaluation of ATM Networks
Jorge García-Vidal, Olga Casals
1993 conf
Architecture and Protocols for High-Speed Networks
Thomas Apel, Chris Blondia, Olga Casals, Jordi Garcia, Kerstin Uhde
1992 A* conf
INFOCOM
Chris Blondia, Olga Casals
1992 J jnl
Perform. Evaluation
Chris Blondia, Olga Casals
1992 J jnl
Ann. Oper. Res.
Jorge García, Olga Casals
1991 conf
MMB
Chris Blondia, Olga Casals
1991 conf
Performance of Distributed Systems and Integrated Communication Networks
Jorge García-Vidal, Olga Casals
redb/extractors/decompiler/bninja/arch/x86.py
← Index redb/extractors/decompiler/bninja/arch/x86.py python
from binaryninja.enums import (
    InstructionTextTokenType,
)

# Support both package and standalone imports
try:
    from .architecture import Architecture
except ImportError:
    # Fallback to absolute imports (for multiprocessing spawned processes)
    from redb.extractors.decompiler.bninja.arch.architecture import Architecture


class Arch_x86(Architecture):
    """The concrete class for architecture-dependent details for x86_64"""

    def __init__(self):
        # general purpose registers for 64bits
        self.gpr_64 = [
            "RAX",
            "RBX",
            "RCX",
            "RDX",
            "RSI",
            "RDIR9",
            "R10",
            "R11",
            "R12",
            "R13",
            "R14",
            "R15",
        ]

        self.gpr_32 = [
            "EAX",
            "EBX",
            "ECX",
            "EDX",
            "ESI",
            "EDI",
            "R8D",
            "R9D",
            "R10D",
            "R11D",
            "R12D",
            "R13D",
            "R14D",
            "R15D",
        ]

        self.gpr_16 = [
            "AX",
            "BX",
            "CX",
            "DX",
            "SI",
            "DI",
            "R8W",
            "R9W",
            "R10W",
            "R11W",
            "R12W",
            "R13W",
            "R14W",
            "R15W",
        ]

        self.gpr_8 = [
            "AL",
            "BL",
            "CL",
            "DL",
            "SIL",
            "DIL",
            "R8B",
            "R9B",
            "R10B",
            "R11B",
            "R12B",
            "R13B",
            "R14B",
            "R15B",
        ]

        self.fpu_x87 = ["ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7"]

        self.sse_xmm = [
            "XMM0",
            "XMM1",
            "XMM2",
            "XMM3",
            "XMM4",
            "XMM5",
            "XMM6",
            "XMM7",
            "XMM8",
            "XMM9",
            "XMM10",
            "XMM11",
            "XMM12",
            "XMM13",
            "XMM14",
            "XMM15",
        ]

        self.avx_ymm = [
            "YMM0",
            "YMM1",
            "YMM2",
            "YMM3",
            "YMM4",
            "YMM5",
            "YMM6",
            "YMM7",
            "YMM8",
            "YMM9",
            "YMM10",
            "YMM11",
            "YMM12",
            "YMM13",
            "YMM14",
            "YMM15",
        ]
        self.flags = ["FLAGS", "EFLAGS", "RFLAGS"]
        self.stack_registers = ["RBP", "RSP", "SP", "BP"]
        self.size = 8
        self.global_registers = (
            self.gpr_64
            + self.gpr_32
            + self.gpr_16
            + self.gpr_8
            + self.fpu_x87
            + self.sse_xmm
            + self.avx_ymm
        )
        self.opcode_categories = self._initialize_opcode_categories()

        ## instructions
        self.instructions = []

    def is_register(self, register):
        register = register.upper()
        return register in self.global_registers

    def is_general_purpose_register(self, register):
        register = register.upper()
        return (
            register in self.gpr_64
            or register in self.gpr_32
            or register in self.gpr_16
            or register in self.gpr_8
        )

    def is_stack_register(self, register):
        register = register.upper()
        return register in self.stack_registers

    def is_xmm_register(self, register):
        register = register.upper()
        return register in self.sse_xmm

    def is_control_flow(self, instr_tokens):
        return False

    def is_control_flow_instruction(self, instr_tokens):
        """Check if an instruction is a control flow instruction (jump, call, return, loop)."""
        try:
            # Extract the mnemonic from the instruction tokens
            mnemonic = None
            for token in instr_tokens:
                if token.type == InstructionTextTokenType.InstructionToken:
                    mnemonic = token.text.upper()
                    break

            if not mnemonic:
                return False

            # Check if it's a jump, call, return, or loop instruction
            return (
                mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
                or mnemonic == "CALL"  # Function calls
                or mnemonic == "RET"  # Return
                or mnemonic == "RETN"  # Another form of return
                or mnemonic.startswith("LOOP")
            )  # Loop instructions

        except Exception as e:
            print(e)
            # If we can't determine, assume it's not a control flow instruction
            return False

    def is_control_flow_instruction_by_mnemonic(self, mnemonic):
        """Check if an instruction is a control flow instruction based on its mnemonic."""
        if not mnemonic:
            return False

        mnemonic = mnemonic.upper()
        return (
            mnemonic.startswith("J")  # All jumps (JMP, JE, JNE, etc.)
            or mnemonic == "CALL"  # Function calls
            or mnemonic == "RET"  # Return
            or mnemonic == "RETN"  # Another form of return
            or mnemonic.startswith("LOOP")
        )

    def _initialize_opcode_categories(self):
        """Initialize mapping of opcodes to categories similar to Ghidra's implementation."""
        opcode_categories = {}
        opcode_index = {}  # Add this to mimic Ghidra's opcodeIndex

        # Define common opcodes array similar to Ghidra's COMMON_OPCODES
        COMMON_OPCODES = [
            # Core instructions (tracked individually)
            "MOV",
            "PUSH",
            "POP",
            "LEA",
            "CALL",
            "RET",  # Data movement and control
            "ADD",
            "SUB",
            "MUL",
            "DIV",  # Basic arithmetic
            "AND",
            "OR",
            "XOR",
            "NOT",  # Logical operations
            "JMP",
            "JE",
            "JNE",  # Basic jumps
            "TEST",
            "CMP",  # Comparisons
            # Grouped categories (aggregated tracking)
            "SIMD_MOVE",  # MOVAPS, MOVDQA, MOVDQU, etc.
            "COND_JUMP_EXT",  # Other conditional jumps (JG, JL, JGE, etc.)
            "STRING_OP",  # MOVS, STOS, LODS, SCAS, CMPS
            "STACK_ADV",  # ENTER, LEAVE, PUSHA, POPA
            "ARITHMETIC_ADV",  # IMUL, IDIV, ADC, SBB
            "BIT_OP",  # SHL, SHR, SAR, ROL, ROR, etc.
            "FPU_OP",  # FLD, FST, FADD, etc.
            "SYSTEM_OP",  # SYSCALL, INT, SYSENTER
            "CRYPTO_OP",  # AES*, SHA* instructions
            "MISC_OP",  # Rare but interesting (CPUID, RDTSC, etc.)
        ]

        # Create index map like Ghidra
        for i, opcode in enumerate(COMMON_OPCODES):
            opcode_index[opcode] = i

        # Now categorize opcodes using if/elif/else structure like in Ghidra
        for opcode in COMMON_OPCODES:
            # String Operations (checking these first to avoid MOV confusion)
            if opcode.startswith("MOVS") or opcode in [
                "STOS",
                "LODS",
                "SCAS",
                "CMPS",
                "REP",
                "REPE",
                "REPNE",
            ]:
                opcode_categories[opcode] = "STRING_MANIPULATION"

            # Data Movement (after string ops to avoid MOVS confusion)
            elif opcode.startswith("MOV") or opcode in ["LEA", "XCHG"]:
                opcode_categories[opcode] = "DATA_MOVEMENT"

            # Stack Operations
            elif opcode in ["PUSH", "POP", "ENTER", "LEAVE", "PUSHA", "POPA"]:
                opcode_categories[opcode] = "STACK_MANAGEMENT"

            # Control Flow (non-conditional)
            elif opcode in ["JMP", "CALL", "RET"]:
                opcode_categories[opcode] = "CONTROL_FLOW"

            # Conditional Jumps and Loops
            elif opcode.startswith("J") or opcode.startswith("LOOP"):
                opcode_categories[opcode] = "CONDITIONAL_JUMP"

            # Arithmetic
            elif opcode in [
                "ADD",
                "SUB",
                "MUL",
                "DIV",
                "IMUL",
                "IDIV",
                "ADC",
                "SBB",
                "INC",
                "DEC",
                "NEG",
            ]:
                opcode_categories[opcode] = "ARITHMETIC"

            # Logical
            elif opcode in ["AND", "OR", "XOR", "NOT", "TEST", "CMP"]:
                opcode_categories[opcode] = "LOGICAL"

            # Shifts & Rotates
            elif opcode in ["SHL", "SHR", "SAR", "SAL", "ROL", "ROR", "RCL", "RCR"]:
                opcode_categories[opcode] = "SHIFT_ROTATE"

            # System & Interrupts
            elif opcode in [
                "SYSCALL",
                "INT",
                "SYSENTER",
                "SYSEXIT",
                "SGDT",
                "SIDT",
                "SLDT",
                "WRMSR",
                "RDMSR",
            ]:
                opcode_categories[opcode] = "SYSTEM_CALLS"

            # Floating Point
            elif opcode.startswith("F"):
                opcode_categories[opcode] = "FPU_ARITHMETIC"

            # System Information and Random Number Generation
            elif opcode in ["PUSHF", "POPF", "CPUID", "RDTSC", "RDRAND", "RDSEED"]:
                opcode_categories[opcode] = "CPU_FEATURES"

            # Cryptography
            elif opcode.startswith("AES") or opcode.startswith("SHA"):
                opcode_categories[opcode] = "CRYPTOGRAPHIC"

            # Miscellaneous (including flag operations)
            else:
                opcode_categories[opcode] = "MISC"

        # Additional categorization for opcodes not in COMMON_OPCODES
        # This can be used in the normalize_opcode method

        # Store both maps as instance variables
        # self.opcode_categories = opcode_categories
        self.opcode_index = opcode_index

        return opcode_categories

    def is_simd_register(self, register):
        return register in self.sse_xmm