Okihiko Ishizuka

24 papers C 1Journal 10Unranked 13
YearRankTypeTitle / Venue / Authors
2010 J jnl
Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits.
IEICE Trans. Inf. Syst.
Motoi Inaba, Koichi Tanno, Hiroki Tamura, Okihiko Ishizuka
2005 J jnl
Combiner-Based MOS OTAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Tanno, Kenya Kondo, Okihiko Ishizuka, Takako Toyama
2005 J jnl
Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka
2003 J jnl
Low-Power and Wide-Input Range Voltage Controlled Linear Variable Resistor Using an FG-MOSFET and Its Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Muneo Kushima, Koichi Tanno, Okihiko Ishizuka
2003 J jnl
Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Dasong Zhu, Koichi Tanno, Okihiko Ishizuka
2003 J jnl
Wide-Input Range Variable Resistor Circuit Using an FG-MOSFET.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Muneo Kushima, Koichi Tanno, Okihiko Ishizuka
2002 J jnl
Analog Inverter with Neuron-MOS Transistors and Its Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
2002 — conf
Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits.
ISMVL
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
2001 J jnl
An immune network with interactions between B cells for pattern recognition.
Syst. Comput. Jpn.
Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno
2001 — conf
Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators.
ISMVL
Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
2000 — conf
Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions.
ISMVL
Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka
2000 — conf
Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors.
ISMVL
Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka
1999 — conf
Down Literal Circuit with Neuron-MOS Transistors and Its Applications.
ISMVL
Jing Shen, Koichi Tanno, Okihiko Ishizuka
1998 J jnl
A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications.
IEEE Trans. Computers
Zheng Tang, Okihiko Ishizuka
1998 — conf
Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits.
ISMVL
Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang
1997 — conf
Multiple-Valued Immune Network Model and Its Simulations.
ISMVL
Zheng Tang, Takayuki Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno
1997 — conf
VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products.
ISMVL
Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko
1995 C conf
A Self-Calibrating A/D Converter Using T-Model Neural Network.
ISCAS
Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno
1995 — conf
Learning Multiple-Valued Logic Networks Based on Back Propagation.
ISMVL
Zheng Tang, Okihiko Ishizuka, Koichi Tanno
1993 — conf
Algebraic Properties of a Learning Multiple-Valued Logic Network.
ISMVL
Zheng Tang, Okihiko Ishizuka, Qixin Cao, Hiroki Matsumoto
1993 — conf
Algorithm and Implementation of a Learning Multiple-Valued Logic Network.
ISMVL
Qixin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
1991 — conf
Synthesis of Current-Mode Pass Transistor Networks.
ISMVL
Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto
1990 — conf
On Design of Multiple-Valued Static Random-Access-Memory.
ISMVL
Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto
1977 J jnl
On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements.
IEEE Trans. Computers
Okihiko Ishizuka