Oguz Ergin - RankMe

102 papers A* 11A 9B 1C 12Journal 53Unranked 16

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance. HPCA Oguzhan Canpolat, A. Giray Yaglikçi, Geraldo F. Oliveira, Ataberk Olgun, Nisa Bostanci, Ismail Emir Yuksel, Haocong Luo, Oguz Ergin, Onur Mutlu
2025	J	`jnl`	Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance. CoRR Oguzhan Canpolat, A. Giray Yaglikçi, Geraldo F. Oliveira, Ataberk Olgun, Nisa Bostanci, Ismail Emir Yüksel, Haocong Luo, Oguz Ergin, Onur Mutlu
2025	A	`conf`	EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques. DSN Oguzhan Canpolat, Ataberk Olgun, David Novo, Oguz Ergin, Onur Mutlu
2025	J	`jnl`	EasyDRAM: An FPGA-based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques. CoRR Oguzhan Canpolat, Ataberk Olgun, David Novo, Oguz Ergin, Onur Mutlu
2025	J	`jnl`	Halis: A Hardware-Software Co-Designed Near-Cache Accelerator for Graph Pattern Mining. IEEE Comput. Archit. Lett. Sevval Izmirli, Julian Pavon, Iván Vargas Valdivieso, Betül Aydeger, Kerem Yalçinkaya, Adrián Cristal, Oguz Ergin, Osman S. Unsal
2025	A*	`conf`	Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. HPCA Yahya Can Tugrul, A. Giray Yaglikçi, Ismail Emir Yüksel, Ataberk Olgun, Oguzhan Canpolat, Nisa Bostanci, Mohammad Sadrosadati, Oguz Ergin, Onur Mutlu
2025	J	`jnl`	Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. CoRR Yahya Can Tugrul, A. Giray Yaglikçi, Ismail Emir Yüksel, Ataberk Olgun, Oguzhan Canpolat, Nisa Bostanci, Mohammad Sadrosadati, Oguz Ergin, Onur Mutlu
2024	A*	`conf`	BreakHammer: Enhancing RowHammer Mitigations by Carefully Throttling Suspect Threads. MICRO Oguzhan Canpolat, A. Giray Yaglikçi, Ataberk Olgun, Ismail Emir Yuksel, Yahya Can Tugrul, Konstantinos Kanellopoulos, Oguz Ergin, Onur Mutlu
2024	J	`jnl`	Leveraging Adversarial Detection to Enable Scalable and Low Overhead RowHammer Mitigations. CoRR Oguzhan Canpolat, Abdullah Giray Yaglikçi, Ataberk Olgun, Ismail Emir Yüksel, Yahya Can Tugrul, Konstantinos Kanellopoulos, Oguz Ergin, Onur Mutlu
2024	A*	`conf`	QUETZAL: Vector Acceleration Framework for Modern Genome Sequence Analysis Algorithms. ISCA Julian Pavon, Iván Vargas Valdivieso, Carlos Rojas, César Hernández, Mehmet Aslan, Roger Figueras, Yichao Yuan, Joël Lindegger, Mohammed Alser, Francesc Moll, Santiago Marco-Sola, Oguz Ergin, Nishil Talati, Onur Mutlu, Osman S. Unsal, Mateo Valero, Adrián Cristal
2024	J	`jnl`	Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture. ACM Trans. Archit. Code Optim. Ataberk Olgun, F. Nisa Bostanci, Geraldo Francisco de Oliveira Junior, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu
2024	J	`jnl`	Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance. CoRR Oguzhan Canpolat, A. Giray Yaglikçi, Geraldo F. Oliveira, Ataberk Olgun, Oguz Ergin, Onur Mutlu
2023	B	`conf`	DEV-PIM: Dynamic Execution Validation with Processing-in-Memory. ETS Alperen Bolat, Yahya Can Tugrul, Seyyid Hikmet Çelik, Sakir Sezer, Marco Ottavi, Oguz Ergin
2023	J	`jnl`	DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ataberk Olgun, Hasan Hassan, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu
2023	J	`jnl`	PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. ACM Trans. Archit. Code Optim. Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	Can We Trust Undervolting in FPGA-Based Deep Learning Designs at Harsh Conditions? IEEE Micro Fahrettin Koc, Behzad Salami, Oguz Ergin, Osman S. Unsal, Adrián Cristal Kestelman
2022	A*	`conf`	Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks. USENIX Security Symposium Daniel Townley, Kerem Arikan, Yu David Liu, Dmitry Ponomarev, Oguz Ergin
2022	A*	`conf`	DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators. HPCA F. Nisa Bostanci, Ataberk Olgun, Lois Orosa, Abdullah Giray Yaglikçi, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators. CoRR Nisa Bostanci, Ataberk Olgun, Lois Orosa, Abdullah Giray Yaglikçi, Jeremie S. Kim, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. CoRR Ataberk Olgun, Hasan Hassan, Abdullah Giray Yaglikçi, Yahya Can Tugrul, Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, Onur Mutlu
2022	A	`conf`	ERIC: An Efficient and Practical Software Obfuscation Framework. DSN Alperen Bolat, Seyyid Hikmet Çelik, Ataberk Olgun, Oguz Ergin, Marco Ottavi
2022	J	`jnl`	ERIC: An Efficient and Practical Software Obfuscation Framework. CoRR Alperen Bolat, Seyyid Hikmet Çelik, Ataberk Olgun, Oguz Ergin, Marco Ottavi
2022	A*	`conf`	HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. MICRO Abdullah Giray Yaglikçi, Ataberk Olgun, Minesh Patel, Haocong Luo, Hasan Hassan, Lois Orosa, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. CoRR Abdullah Giray Yaglikçi, Ataberk Olgun, Minesh Patel, Haocong Luo, Hasan Hassan, Lois Orosa, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ismail Emir Yüksel, Behzad Salami, Oguz Ergin, Osman Sabri Unsal, Adrián Cristal Kestelman
2022	—	`conf`	PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques. ISVLSI Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques. CoRR Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE Trans. Very Large Scale Integr. Syst. Kerem Arikan, Alessandro Palumbo, Luca Cassano, Pedro Reviriego, Salvatore Pontarelli, Giuseppe Bianchi, Oguz Ergin, Marco Ottavi
2022	J	`jnl`	Sectored DRAM: An Energy-Efficient High-Throughput and Practical Fine-Grained DRAM Architecture. CoRR Ataberk Olgun, F. Nisa Bostanci, Geraldo F. Oliveira, Yahya Can Tugrul, Rahul Bera, Abdullah Giray Yaglikçi, Hasan Hassan, Oguz Ergin, Onur Mutlu
2022	J	`jnl`	TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs. CoRR Ismail Emir Yüksel, Ataberk Olgun, Behzad Salami, F. Nisa Bostanci, Yahya Can Tugrul, Abdullah Giray Yaglikçi, Nika Mansouri-Ghiasi, Onur Mutlu, Oguz Ergin
2021	J	`jnl`	MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs. CoRR Ismail Emir Yüksel, Behzad Salami, Oguz Ergin, Osman Sabri Unsal, Adrián Cristal Kestelman
2021	J	`jnl`	PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM. CoRR Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, Onur Mutlu
2021	A*	`conf`	QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips. ISCA Ataberk Olgun, Minesh Patel, Abdullah Giray Yaglikçi, Haocong Luo, Jeremie S. Kim, Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, Onur Mutlu
2021	J	`jnl`	QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips. CoRR Ataberk Olgun, Minesh Patel, Abdullah Giray Yaglikçi, Haocong Luo, Jeremie S. Kim, Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, Onur Mutlu
2020	—	`conf`	A Microprocessor Protection Architecture against Hardware Trojans in Memories. DTIS Alperen Bolat, Luca Cassano, Pedro Reviriego, Oguz Ergin, Marco Ottavi
2020	A	`conf`	An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration. DSN Behzad Salami, Erhan Baturay Onural, Ismail Emir Yuksel, Fahrettin Koc, Oguz Ergin, Adrián Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad, Onur Mutlu
2020	J	`jnl`	An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration. CoRR Behzad Salami, Erhan Baturay Onural, Ismail Emir Yuksel, Fahrettin Koc, Oguz Ergin, Adrián Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad, Onur Mutlu
2019	—	`conf`	A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees. HPCS Oyku Melikoglu, Oguz Ergin, Behzad Salami, Julian Pavon, Osman S. Unsal, Adrián Cristal
2019	J	`jnl`	A Novel FPGA-Based High Throughput Accelerator For Binary Search Trees. CoRR Oyku Melikoglu, Oguz Ergin, Behzad Salami, Julian Pavon, Osman S. Unsal, Adrián Cristal
2018	J	`jnl`	Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency. CoRR Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu
2018	J	`jnl`	GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies. BMC Genom. Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, Onur Mutlu
2018	J	`jnl`	Opcode vector: An efficient scheme to detect soft errors in instructions. Microelectron. Reliab. Jorge Martínez, Mert Atamaner, Pedro Reviriego, Oguz Ergin, Marco Ottavi
2018	J	`jnl`	SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure. CoRR Hasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu
2017	—	`conf`	Detecting errors in instructions with bloom filters. DFT Mert Atamaner, Oguz Ergin, Marco Ottavi, Pedro Reviriego
2017	J	`jnl`	GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies. CoRR Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, Onur Mutlu
2017	J	`jnl`	GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping. Bioinform. Mohammed Alser, Hasan Hassan, Hongyi Xin, Oguz Ergin, Onur Mutlu, Can Alkan
2017	A*	`conf`	SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies. HPCA Hasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu
2016	A*	`conf`	ChargeCache: Reducing DRAM latency by exploiting row access locality. HPCA Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu
2016	—	`conf`	Error recovery through partial value similarity. DFT Abdulaziz Eker, Oguz Ergin
2016	J	`jnl`	Exploiting Existing Copies in Register File for Soft Error Correction. IEEE Comput. Archit. Lett. Abdulaziz Eker, Oguz Ergin
2016	J	`jnl`	GateKeeper: Enabling Fast Pre-Alignment in DNA Short Read Mapping with a New Streaming Accelerator Architecture. CoRR Mohammed Alser, Hasan Hassan, Hongyi Xin, Oguz Ergin, Onur Mutlu, Can Alkan
2016	J	`jnl`	URFA-Update based register file architecture with partial register write for energy efficiency. Microprocess. Microsystems Abdulaziz Eker, Yakup Murat Mert, Oguz Ergin
2015	A	`conf`	User-specific skin temperature-aware DVFS for smartphones. DATE Begum Egilmez, Gokhan Memik, Seda Ogrenci Memik, Oguz Ergin
2015	—	`conf`	Using value similarity of registers for soft error mitigation. DFTS Abdulaziz Eker, Oguz Ergin
2014	J	`jnl`	Bit Impact Factor: Towards making fair vulnerability comparison. Microprocess. Microsystems Serdar Zafer Can, Gulay Yalcin, Oguz Ergin, Osman Sabri Unsal, Adrián Cristal
2014	J	`jnl`	Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection. ACM Trans. Archit. Code Optim. Gulay Yalcin, Oguz Ergin, Emrah Islek, Osman Sabri Unsal, Adrián Cristal
2014	J	`jnl`	Exploiting Virtual Addressing for Increasing Reliability. IEEE Comput. Archit. Lett. Yaman Cakmakci, Oguz Ergin
2014	C	`conf`	Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches. IOLTS Gulay Yalcin, Emrah Islek, Oyku Tozlu, Pedro Reviriego, Adrián Cristal, Osman S. Unsal, Oguz Ergin
2014	J	`jnl`	Exploiting processor features to implement error detection in reduced precision matrix multiplications. Microprocess. Microsystems Pedro Reviriego, Serdar Zafer Can, Çagri Eryilmaz, Juan Antonio Maestro, Oguz Ergin
2014	—	`conf`	GPU based Parallel Image Processing Library for Embedded Systems. VISAPP (1) Mustafa Cavus, Hakki Doganer Sumerkan, Osman Seckin Simsek, Hasan Hassan, Abdullah Giray Yaglikçi, Oguz Ergin
2013	C	`conf`	Adapting the columns of storage components for lower static energy dissipation. VLSI-SoC Mehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin
2013	J	`jnl`	Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values. IEEE Comput. Archit. Lett. Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, Juan Antonio Maestro
2013	A	`conf`	Exploiting replicated checkpoints for soft error detection and correction. DATE Fahrettin Koc, Kenan Bozdas, Burak Karsli, Oguz Ergin
2012	C	`conf`	Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to Electromigration. DSD Mehmet Kayaalp, Fahrettin Koc, Oguz Ergin
2012	C	`conf`	Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In Comparators. DSD Mehmet Kayaalp, Fahrettin Koc, Oguz Ergin
2011	—	`conf`	Tag simplification: Achieving power efficiency through reducing the complexity of the wakeup logic. ICEAC Mehmet Burak Aykenar, Muhammet Ozgur, Vehbi Esref Bayraktar, Oguz Ergin
2011	C	`conf`	Using content-aware bitcells to reduce static energy dissipation. ICCD Fahrettin Koc, Osman Seckin Simsek, Oguz Ergin
2010	—	`conf`	Complexity-Effective Rename Table Design for Rapid Speculation Recovery. ARCS Görkem Asilioglu, Emine Merve Kaya, Oguz Ergin
2010	C	`conf`	Dynamic register file partitioning in superscalar microprocessors for energy efficiency. ICCD Meltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp, Oguz Ergin
2010	—	`conf`	Exploiting Inactive Rename Slots for Detecting Soft Errors. ARCS Mehmet Kayaalp, Oguz Ergin, Osman S. Ünsal, Mateo Valero
2010	J	`jnl`	Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands. J. Circuits Syst. Comput. Ilknur Cansu Kaynak, Yusuf Onur Koçberber, Oguz Ergin
2009	J	`jnl`	Energy-efficient register caching with compiler assistance. ACM Trans. Archit. Code Optim. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2009	J	`jnl`	Exploring the limits of early register release: Exploiting compiler analysis. ACM Trans. Archit. Code Optim. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2009	J	`jnl`	Modifying the Data-Holding Components of the Microprocessors for Energy Efficiency. J. Circuits Syst. Comput. Yusuf Osmanlioglu, Y. Sinan Hanay, Oguz Ergin
2009	J	`jnl`	Reducing Soft Errors through Operand Width Aware Policies. IEEE Trans. Dependable Secur. Comput. Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
2009	—	`conf`	Reducing parity generation latency through input value aware circuits. ACM Great Lakes Symposium on VLSI Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin
2008	J	`jnl`	Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz
2007	C	`conf`	Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. IOLTS Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González
2007	J	`jnl`	Using Tag-Match Comparators for Detecting Soft Errors. IEEE Comput. Archit. Lett. Gulay Yalcin, Oguz Ergin
2006	J	`jnl`	Early Register Deallocation Mechanisms Using Checkpointed Register Files. IEEE Trans. Computers Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
2006	A	`conf`	Empowering a helper cluster through data-width aware instruction selection policies. IPDPS Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González
2006	—	`conf`	Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors. PATMOS Oguz Ergin
2006	J	`jnl`	Exploiting Narrow Values for Soft Error Tolerance. IEEE Comput. Archit. Lett. Oguz Ergin, Osman S. Unsal, Xavier Vera, Antonio González
2006	J	`jnl`	Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
2006	J	`jnl`	Instruction packing: Toward fast and energy-efficient instruction scheduling. ACM Trans. Archit. Code Optim. Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
2005	—	`conf`	Compiler Directed Early Register Release. IEEE PACT Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
2005	A	`conf`	Instruction packing: reducing power and delay of the dynamic scheduling logic. ISLPED Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin
2005	C	`conf`	Power-Efficient Wakeup Tag Broadcast. ICCD Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
2004	J	`jnl`	Complexity-Effective Reorder Buffer Designs for Superscalar Processors. IEEE Trans. Computers Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
2004	C	`conf`	Defining Wakeup Width for Efficient Dynamic Scheduling. ICCD Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
2004	J	`jnl`	Energy Efficient Comparators for Superscalar Datapaths. IEEE Trans. Computers Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
2004	C	`conf`	Increasing Processor Performance Through Early Register Release. ICCD Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose
2004	J	`jnl`	Isolating Short-Lived Operands for Energy Reduction. IEEE Trans. Computers Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
2004	—	`conf`	Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. PACS Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
2004	A*	`conf`	Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. MICRO Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev
2003	C	`conf`	Distributed Reorder Buffer Schemes for Low Power. ICCD Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
2003	—	`conf`	Energy Efficient Register Renaming. PATMOS Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
2003	J	`jnl`	Energy-efficient issue queue design. IEEE Trans. Very Large Scale Integr. Syst. Dmitry V. Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter M. Kogge
2003	A	`conf`	Power efficient comparators for long arguments in superscalar processors. ISLPED Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
2003	—	`conf`	Reducing Datapath Energy through the Isolation of Short-Lived Operands. IEEE PACT Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
2003	A	`conf`	Reducing reorder buffer complexity through selective operand caching. ISLPED Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
2002	C	`conf`	A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. ICCD Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev