Odysseas Zografos

27 papers A* 1A 5C 2Journal 5Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers. IEEE Trans. Circuits Syst. I Regul. Pap. Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru
2025	A	`conf`	Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node. ICCAD Halil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert
2025	J	`jnl`	Iterative Layout-Aware Power, Thermal, and IR-Drop Co-Optimization: Ensuring Convergency in 3D-ICs. IEEE J. Emerg. Sel. Topics Circuits Syst. Mohamed Naeim, Dwaipayan Biswas, Yun Dai, Odysseas Zografos, Herman Oprins, Geert Van der Plas, CT Kao, Pinhong Chen, Dragomir Milojevic
2024	—	`conf`	Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert
2024	A*	`conf`	GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
2024	—	`conf`	Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2024	—	`conf`	Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2023	—	`conf`	Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
2023	—	`conf`	Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert
2022	—	`conf`	Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
2022	J	`jnl`	Challenges and targets of MRAM-enabled scaled spintronic logic circuits. CoRR Fanfan Meng, Florin Ciubotaru, S.-Y. Lee, Odysseas Zografos, M. Gupta, Van D. Nguyen, Sebastien Couet, Gouri Sankar Kar, Giovanni De Micheli, Christoph Adelmann, Inge Asselberghs
2022	A	`conf`	Design enablement of CFET devices for sub-2nm CMOS nodes. DATE Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert
2022	J	`jnl`	Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert
2022	—	`conf`	Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne
2022	—	`conf`	System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu
2021	—	`conf`	A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes
2021	—	`conf`	Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm. IRPS Subrat Mishra, Pieter Weckx, Odysseas Zografos, Ji-Yung Lin, Alessio Spessot, Francky Catthoor
2020	A	`conf`	Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper). DATE Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli
2018	A	`conf`	Majority logic synthesis. ICCAD Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken
2017	—	`conf`	Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. ISVLSI Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli
2017	A	`conf`	Wave pipelining for majority-based beyond-CMOS technologies. DATE Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins
2016	—	`conf`	Inversion optimization in Majority-Inverter Graphs. NANOARCH Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2016	J	`jnl`	Non-volatile spin wave majority gate at the nanoscale. CoRR Odysseas Zografos, Sourav Dutta, Mauricio Manfrini, Adrien Vaysset, Bart Sorée, Azad Naeemi, Praveen Raghavan, Rudy Lauwereins, Iuliana P. Radu
2015	—	`conf`	Area and routing efficiency of SWD circuits compared to advanced CMOS. ICICDT Odysseas Zografos, Praveen Raghavan, Yasser Sherazi, Adrien Vaysset, Florin Ciubotaru, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Aaron Thean
2014	C	`conf`	Majority Logic Synthesis for Spin Wave Technology. DSD Odysseas Zografos, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Praveen Raghavan, Giovanni De Micheli
2014	C	`conf`	Novel grid-based power routing scheme for regular controllable-polarity FET arrangements. ISCAS Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2014	—	`conf`	System-level assessment and area evaluation of Spin Wave logic circuits. NANOARCH Odysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana P. Radu, Diederik Verkest, Aaron Thean