Nur A. Touba - RankMe

162 papers A* 1A 28B 1C 8Misc 39Journal 35Unranked 49

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Multi-Modal Attention-Based Framework for Good Die in Bad Neighborhood Methodology. DFT Mohammad Ershad Shaik, Abhishek Kumar Mishra, Nagarajan Kandasamy, Nur A. Touba
2025	—	`conf`	Double Column Error Correction in RRAM Matrix Multiplication Using Weighted Checksums. LATS Krishnaja Kodali, Kenrick Xavier Pinto, Abhishek Das, Nur A. Touba
2024	C	`conf`	Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums. IOLTS Kenrick Xavier Pinto, Krishnaja Kodali, Abhishek Das, Nur A. Touba
2024	Misc	`conf`	WaferCap: Open Classification of Wafer Map Patterns using Deep Capsule Network. VTS Abhishek Kumar Mishra, Mohammad Ershad Shaik, Anush Niranjan Lingamoorthy, Suman Kumar, Anup Das, Nagarajan Kandasamy, Nur A. Touba
2023	—	`conf`	Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder. DFT Shruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba
2022	J	`jnl`	CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM. IEEE Trans. Computers Muhammad Imran, Taehyun Kwon, Nur A. Touba, Joon-Sung Yang
2020	J	`jnl`	A New Class of Single Burst Error Correcting Codes with Parallel Decoding. IEEE Trans. Computers Abhishek Das, Nur A. Touba
2020	Misc	`conf`	Selective Checksum based On-line Error Correction for RRAM based Matrix Operations. VTS Abhishek Das, Nur A. Touba
2019	Misc	`conf`	A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation. VTS Abhishek Das, Nur A. Touba
2019	Misc	`conf`	Layered-ECC: A Class of Double Error Correcting Codes for High Density Memory Systems. VTS Abhishek Das, Nur A. Touba
2019	—	`conf`	Online Correction of Hard Errors and Soft Errors via One-Step Decodable OLS Codes for Emerging Last Level Caches. LATS Abhishek Das, Nur A. Touba
2018	—	`conf`	Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs. DFT Abhishek Das, Nur A. Touba
2018	—	`conf`	Low Complexity Burst Error Correcting Codes to Correct MBUs in SRAMs. ACM Great Lakes Symposium on VLSI Abhishek Das, Nur A. Touba
2018	Misc	`conf`	Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decoding. VTS Abhishek Das, Nur A. Touba
2017	—	`conf`	Computing with obfuscated data in arbitrary logic circuits via noise insertion and cancellation. DSC Yu-Wei Lee, Nur A. Touba
2017	J	`jnl`	Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Taehee Lee, Nur A. Touba, Joon-Sung Yang
2017	J	`jnl`	Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hyunseung Han, Nur A. Touba, Joon-Sung Yang
2017	—	`conf`	Improving test compression with multiple-polynomial LFSRs. DFT Yu-Wei Lee, Nur A. Touba
2017	C	`conf`	Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel Cells. ICCD Abhishek Das, Nur A. Touba
2016	J	`jnl`	Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joon-Sung Yang, Jinsuk Chung, Nur A. Touba
2016	A*	`conf`	Reducing control bit overhead for X-masking/X-canceling hybrid architecture via pattern partitioning. DAC Jin-Hyun Kang, Nur A. Touba, Joon-Sung Yang
2016	A	`conf`	Using symbolic canceling to improve diagnosis from compacted response. ITC Kamran Saleem, Nur A. Touba
2015	—	`conf`	Compacting output responses containing unknowns using an embedded processor. DFTS Kamran Saleem, Sreenivaas S. Muthyala, Nur A. Touba
2015	—	`conf`	Improving X-tolerant combinational output compaction via input rotation. DFTS Asad Amin Bawa, Nur A. Touba
2015	—	`conf`	Improving logic obfuscation via logic cone analysis. LATS Yu-Wei Lee, Nur A. Touba
2014	—	`conf`	Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. VLSI-SoC (Selected Papers) Sreenivaas S. Muthyala, Nur A. Touba
2014	A	`conf`	Improving test compression with scan feedforward techniques. ITC Sreenivaas S. Muthyala, Nur A. Touba
2014	J	`jnl`	Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability. IEEE Trans. Very Large Scale Integr. Syst. Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
2014	C	`conf`	Reducing test time for 3D-ICs by improved utilization of test elevators. VLSI-SoC Sreenivaas S. Muthyala, Nur A. Touba
2014	J	`jnl`	Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joon-Sung Yang, Jinkyu Lee, Nur A. Touba
2013	—	`conf`	Efficient compression of x-masking control data via dynamic channel allocation. DFTS Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba
2013	—	`conf`	Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. DFTS Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta
2013	J	`jnl`	Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Joon-Sung Yang, Nur A. Touba
2013	Misc	`conf`	SOC test compression scheme using sequential linear decompressors with retained free variables. VTS Sreenivaas S. Muthyala, Nur A. Touba
2013	—	`conf`	Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test. DFTS Yu-Wei Lee, Nur A. Touba
2012	J	`jnl`	Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joon-Sung Yang, Nur A. Touba
2012	Misc	`conf`	Exploiting X-correlation in output compression via superset X-canceling. VTS Jinsuk Chung, Nur A. Touba
2012	—	`conf`	Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly. DFT Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
2012	A	`conf`	Improving test compression by retaining non-pivot free variables in sequential linear decompressors. ITC Sreenivaas S. Muthyala, Nur A. Touba
2012	J	`jnl`	Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie
2012	C	`conf`	Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories. VLSI-SoC Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
2012	—	`conf`	Using partial masking in X-chains to increase output compaction for an X-canceling MISR. DFT Asad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba
2012	J	`jnl`	X-Canceling MISR Architectures for Output Response Compaction With Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Joon-Sung Yang, Nur A. Touba
2011	Misc	`conf`	Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. VTS Rudrajit Datta, Nur A. Touba
2011	—	`conf`	Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach. DFT Rudrajit Datta, Nur A. Touba
2011	—	`conf`	X-Stacking - A Method for Reducing Control Data for Output Compaction. DFT Rudrajit Datta, Nur A. Touba
2010	Misc	`conf`	CSER: BISER-based concurrent soft-error resilience. VTS Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li
2010	J	`jnl`	Correlation-Based Rectangular Encoding. IEEE Trans. Very Large Scale Integr. Syst. Jinkyu Lee, Nur A. Touba
2010	—	`conf`	Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. DFT Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
2010	A	`conf`	Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches. ITC Rudrajit Datta, Nur A. Touba
2009	A	`conf`	An industrial case study for X-canceling MISR. ITC Joon-Sung Yang, Nur A. Touba, Shih-Yu Yang, T. M. Mak
2009	Misc	`conf`	Automated Selection of Signals to Observe for Efficient Silicon Debug. VTS Joon-Sung Yang, Nur A. Touba
2009	Misc	`conf`	Exploiting Unused Spare Columns to Improve Memory ECC. VTS Rudrajit Datta, Nur A. Touba
2009	—	`conf`	Improving Memory Repair by Selective Row Partitioning. DFT Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
2009	—	`conf`	Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
2009	A	`conf`	Test point insertion using functional flip-flops to drive control points. ITC Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
2008	A	`ed.`	2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008 ITC Douglas Young, Nur A. Touba
2008	—	`conf`	Enhancing Silicon Debug via Periodic Monitoring. DFT Joon-Sung Yang, Nur A. Touba
2008	Misc	`conf`	Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. VTS Joon-Sung Yang, Nur A. Touba
2008	J	`jnl`	Guest Editorial. J. Electron. Test. Nur A. Touba, Adelio Salsano, Minsu Choi
2008	J	`jnl`	Guest Editors' Introduction: Progress in Test Compression. IEEE Des. Test Comput. Scott Davidson, Nur A. Touba
2008	J	`jnl`	ITC 2008 Highlights. IEEE Des. Test Comput. Nur A. Touba
2008	Misc	`conf`	Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation. VTS Ritesh Garg, Richard Putman, Nur A. Touba
2007	—	`ed.`	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. DFT Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba
2007	J	`jnl`	LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinkyu Lee, Nur A. Touba
2007	Misc	`conf`	Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code. VTS Avijit Dutta, Nur A. Touba
2007	J	`jnl`	Relationship Between Entropy and Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kedarnath J. Balakrishnan, Nur A. Touba
2007	—	`conf`	Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code. DFT Avijit Dutta, Nur A. Touba
2007	Misc	`conf`	Using Multiple Expansion Ratios and Dependency Analysis to Improve Test Compression. VTS Richard Putman, Nur A. Touba
2007	A	`conf`	X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR. ITC Nur A. Touba
2006	Misc	`conf`	Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. VTS Jinkyu Lee, Nur A. Touba
2006	J	`jnl`	Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits. IEEE Trans. Very Large Scale Integr. Syst. Eric W. MacDonald, Nur A. Touba
2006	—	`conf`	Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition. ATS Jinkyu Lee, Nur A. Touba
2006	J	`jnl`	Improving Linear Test Data Compression. IEEE Trans. Very Large Scale Integr. Syst. Kedarnath J. Balakrishnan, Nur A. Touba
2006	Misc	`conf`	Iterative OPDD Based Signal Probability Calculation. VTS Avijit Dutta, Nur A. Touba
2006	J	`jnl`	Survey of Test Vector Compression Techniques. IEEE Des. Test Comput. Nur A. Touba
2006	—	`conf`	Synthesis of Efficient Linear Test Pattern Generators. DFT Avijit Dutta, Nur A. Touba
2006	A	`conf`	Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. ITC Avijit Dutta, Nur A. Touba
2005	—	`conf`	Compressing Functional Tests for Microprocessors. Asian Test Symposium Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
2005	—	`conf`	Low Cost Test Vector Compression/Decompression Scheme for Circuits with a Reconfigurable Serial Multiplier. ISVLSI Avijit Dutta, Terence Rodrigues, Nur A. Touba
2005	—	`conf`	Low Power BIST Based on Scan Partitioning. DFT Jinkyu Lee, Nur A. Touba
2005	A	`conf`	Methods for improving test compression. ITC Nur A. Touba
2005	A	`conf`	Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE Kedarnath J. Balakrishnan, Nur A. Touba
2005	J	`jnl`	Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits. J. Low Power Electron. Shalini Ghosh, Sugato Basu, Nur A. Touba
2005	Misc	`conf`	Synthesis of Low Power CED Circuits Based on Parity Codes. VTS Shalini Ghosh, Sugato Basu, Nur A. Touba
2005	A	`conf`	Synthesis of nonintrusive concurrent error detection using an even error detecting function. ITC Avijit Dutta, Nur A. Touba
2005	—	`conf`	Using Statistical Transformations to Improve Compression for Linear Decompressors. DFT Samuel I. Ward, Chris Schattauer, Nur A. Touba
2004	Misc	`conf`	3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. VTS C. V. Krishna, Nur A. Touba
2004	J	`jnl`	Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. C. V. Krishna, Abhijit Jas, Nur A. Touba
2004	A	`conf`	Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC Kedarnath J. Balakrishnan, Nur A. Touba
2004	C	`conf`	Low Power Test Data Compression Based on LFSR Reseeding. ICCD Jinkyu Lee, Nur A. Touba
2004	—	`conf`	Low-power weighted pseudo-random BIST using special scan cells. ACM Great Lakes Symposium on VLSI Shalini Ghosh, Eric W. MacDonald, Sugato Basu, Nur A. Touba
2004	J	`jnl`	Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. Very Large Scale Integr. Syst. Kartik Mohanram, Nur A. Touba
2004	J	`jnl`	Matrix-based software test data decompression for systems-on-a-chip. J. Syst. Archit. Kedarnath J. Balakrishnan, Nur A. Touba
2004	A	`conf`	Reducing Power Consumption in Memory ECC Checkers. ITC Shalini Ghosh, Nur A. Touba, Sugato Basu
2004	B	`conf`	Relating entropy theory to test data compression. ETS Kedarnath J. Balakrishnan, Nur A. Touba
2004	J	`jnl`	Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. Very Large Scale Integr. Syst. Abhijit Jas, Bahram Pouya, Nur A. Touba
2004	J	`jnl`	Weighted pseudorandom hybrid BIST. IEEE Trans. Very Large Scale Integr. Syst. Abhijit Jas, C. V. Krishna, Nur A. Touba
2003	A	`conf`	Adjustable Width Linear Combinational Scan Vector Decompression. ICCAD C. V. Krishna, Nur A. Touba
2003	J	`jnl`	An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
2003	A	`conf`	Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC Kartik Mohanram, Nur A. Touba
2003	Misc	`conf`	Deterministic Test Vector Decompression in Software Using Linear Operations. VTS Kedarnath J. Balakrishnan, Nur A. Touba
2003	Misc	`conf`	Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS Kartik Mohanram, Nur A. Touba
2003	—	`conf`	Hybrid BIST Using an Incrementally Guided LFSR. DFT C. V. Krishna, Nur A. Touba
2003	—	`conf`	Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. ISVLSI Shalini Ghosh, Sugato Basu, Nur A. Touba
2003	—	`conf`	Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT Kartik Mohanram, Nur A. Touba
2003	—	`conf`	Scan-Based BIST Diagnosis Using an Embedded Processor. DFT Kedarnath J. Balakrishnan, Nur A. Touba
2003	C	`conf`	Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
2003	J	`jnl`	Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans. Design Autom. Electr. Syst. Lei Li, Krishnendu Chakrabarty, Nur A. Touba
2002	—	`conf`	A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) Kartik Mohanram, C. V. Krishna, Nur A. Touba
2002	J	`jnl`	Circular BIST with state skipping. IEEE Trans. Very Large Scale Integr. Syst. Nur A. Touba
2002	Misc	`conf`	Controlling Peak Power During Scan Testing. VTS Ranganathan Sankaralingam, Nur A. Touba
2002	J	`jnl`	Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. J. Electron. Test. Abhijit Jas, Nur A. Touba
2002	—	`conf`	Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT Kartik Mohanram, Nur A. Touba
2002	—	`conf`	Inserting Test Points to Control Peak Power During Scan Testing. DFT Ranganathan Sankaralingam, Nur A. Touba
2002	—	`conf`	Matrix-Based Test Vector Decompression Using an Embedded Processor. DFT Kedarnath J. Balakrishnan, Nur A. Touba
2002	A	`conf`	Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression. ITC C. V. Krishna, Nur A. Touba
2002	—	`conf`	Reducing Test Power During Test Using Programmable Scan Chain Disable. DELTA Ranganathan Sankaralingam, Nur A. Touba
2002	Misc	`conf`	Very Low Voltage Testing of SOI Integrated Circuits. VTS Eric W. MacDonald, Nur A. Touba
2001	J	`jnl`	Bit-fixing in pseudorandom sequences for scan BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nur A. Touba, Edward J. McCluskey
2001	Misc	`conf`	Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS Abhijit Jas, C. V. Krishna, Nur A. Touba
2001	—	`conf`	Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability. DFT Jayabrata Ghosh-Dastidar, Nur A. Touba
2001	Misc	`conf`	Reducing Power Dissipation during Test Using Scan Chain Disable. VTS Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya
2001	A	`conf`	Test vector encoding using partial LFSR reseeding. ITC C. V. Krishna, Abhijit Jas, Nur A. Touba
2000	Misc	`conf`	A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan Chains. VTS Jayabrata Ghosh-Dastidar, Nur A. Touba
2000	—	`conf`	Diagnosing resistive bridges using adaptive techniques. CICC Jayabrata Ghosh-Dastidar, Nur A. Touba
2000	—	`conf`	Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. IOLTW Debaleena Das, Nur A. Touba, Markus Seuring, Michael Gössel
2000	A	`conf`	Reducing test data volume using external/LBIST hybrid test patterns. ITC Debaleena Das, Nur A. Touba
2000	Misc	`conf`	Static Compaction Techniques to Control Scan Vector Power Dissipation. VTS Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba
2000	—	`conf`	Testing domino circuits in SOI technology. Asian Test Symposium Eric W. MacDonald, Nur A. Touba
2000	Misc	`conf`	Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS Abhijit Jas, Bahram Pouya, Nur A. Touba
1999	Misc	`conf`	A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. VLSI Design Debaleena Das, Nur A. Touba
1999	Misc	`conf`	Adaptive Techniques for Improving Delay Fault Diagnosis. VTS Jayabrata Ghosh-Dastidar, Nur A. Touba
1999	—	`conf`	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium Abhijit Jas, Kartik Mohanram, Nur A. Touba
1999	—	`conf`	Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) W. Quddus, Abhijit Jas, Nur A. Touba
1999	A	`conf`	Delay testing of SOI circuits: Challenges with the history effect. ITC Eric W. MacDonald, Nur A. Touba
1999	A	`conf`	Fault diagnosis in scan-based BIST using both time and space information. ITC Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. Touba
1999	—	`conf`	Observing test response of embedded cores through surrounding logic. ISCAS (1) P. K. Jaini, Nur A. Touba
1999	J	`jnl`	RP-SYN: synthesis of random pattern testable circuits with test point insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nur A. Touba, Edward J. McCluskey
1999	Misc	`conf`	Scan Vector Compression/Decompression Using Statistical Coding. VTS Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba
1999	J	`jnl`	Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. J. Electron. Test. Debaleena Das, Nur A. Touba
1999	C	`conf`	Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD Abhijit Jas, Nur A. Touba
1999	Misc	`conf`	Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits. VTS Debaleena Das, Nur A. Touba
1998	—	`conf`	A Systematic Approach for Diagnosing Multiple Delay Faults. DFT Jayabrata Ghosh-Dastidar, Nur A. Touba
1998	A	`conf`	BETSY: synthesizing circuits for a specified BIST environment. ITC Zhe Zhao, Bahram Pouya, Nur A. Touba
1998	—	`conf`	Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. Asian Test Symposium Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich
1998	Misc	`conf`	Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes. VTS Debaleena Das, Nur A. Touba
1998	Misc	`conf`	Synthesis of Zero-Aliasing Elementary-Tree Space Compactors. VTS Bahram Pouya, Nur A. Touba
1998	A	`conf`	Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC Abhijit Jas, Nur A. Touba
1997	J	`jnl`	Logic synthesis of multilevel circuits with concurrent error detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nur A. Touba, Edward J. McCluskey
1997	A	`conf`	Modifying User-Defined Logic for Test Access to Embedded Cores. ITC Bahram Pouya, Nur A. Touba
1997	Misc	`conf`	Obtaining High Fault Coverage with Circular BIST Via State Skipping. VTS Nur A. Touba
1997	C	`conf`	Pseudo-Random Pattern Testing of Bridging Faults. ICCD Nur A. Touba, Edward J. McCluskey
1997	Misc	`conf`	Testing Embedded Cores Using Partial Isolation Rings. VTS Nur A. Touba, Bahram Pouya
1997	J	`jnl`	Using Partial Isolation Rings to Test Core-Based Designs. IEEE Des. Test Comput. Nur A. Touba, Bahram Pouya
1996	A	`conf`	Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. ITC Nur A. Touba, Edward J. McCluskey
1996	Misc	`conf`	Applying two-pattern tests using scan-mapping. VTS Nur A. Touba, Edward J. McCluskey
1996	Misc	`conf`	Test point insertion based on path tracing. VTS Nur A. Touba, Edward J. McCluskey
1995	A	`conf`	Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST. ITC Nur A. Touba, Edward J. McCluskey
1995	Misc	`conf`	Transformed pseudo-random patterns for BIST. VTS Nur A. Touba, Edward J. McCluskey
1994	A	`conf`	Automated Logic Synthesis of Random-Pattern-Testable Circuits. ITC Nur A. Touba, Edward J. McCluskey
1994	A	`conf`	Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection. ICCAD Nur A. Touba, Edward J. McCluskey