Nuo Xu

11 papers B 2Journal 9
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 16-bit 2MSPS pipelined SAR ADC with digital background calibration in 0.18 μm CMOS.
Microelectron. J.
Nuo Xu, Yuhua Liang
2025 J jnl
ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates.
ACM Trans. Design Autom. Electr. Syst.
Nuo Xu, Yihong Hu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang
2024 B conf
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing.
ASPDAC
Yihong Hu, Nuo Xu, Chaochao Feng, Wei Tong, Kang Liu, Liang Fang
2023 J jnl
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device.
ACM Trans. Design Autom. Electr. Syst.
Junwei Zeng, Nuo Xu, Yabo Chen, Chenglong Huang, Zhiwei Li, Liang Fang
2023 J jnl
Rescuing ReRAM-based Neural Computing Systems from Device Variation.
ACM Trans. Design Autom. Electr. Syst.
Chenglong Huang, Nuo Xu, Junwei Zeng, Wenqing Wang, Yihong Hu, Liang Fang, Desheng Ma, Yanting Chen
2022 J jnl
A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure.
IEEE Trans. Circuits Syst. II Express Briefs
Pinyun Yi, Yuhua Liang, Shubin Liu, Nuo Xu, Liang Fang, Yue Hao
2022 J jnl
Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design.
Adv. Intell. Syst.
Zhiwei Li, Hongchang Long, Xi Zhu, Yinan Wang, Haijun Liu, Qingjiang Li, Nuo Xu, Hui Xu
2022 J jnl
MESO-LUT: A design approach of look up tables based on MESO devices.
Microelectron. J.
Junwei Zeng, Nuo Xu, Cheng Li, Desheng Ma, Chenglong Huang, Wenqing Wang, Yihong Hu, Liang Fang
2021 B conf
HDNH: a read-efficient and write-optimized hashing scheme for hybrid DRAM-NVM memory.
ICPP
Junhao Zhu, Kaixin Huang, Xiaomin Zou, Chenglong Huang, Nuo Xu, Liang Fang
2020 J jnl
A Stateful Logic Family Based on a New Logic Primitive Circuit Composed of Two Antiparallel Bipolar Memristors.
Adv. Intell. Syst.
Nuo Xu, Tae Gyun Park, Hae Jin Kim, Xinglong Shao, Kyung Jean Yoon, Tae Hyung Park, Liang Fang, Kyung Min Kim, Cheol Seong Hwang
2020 J jnl
A forming-free ReRAM cell with low operating voltage.
IEICE Electron. Express
Binbin Yang, Nuo Xu, Cheng Li, Chenglong Huang, Desheng Ma, Jiahao Liu, Daniel Arumí, Liang Fang