Nozomu Togawa - RankMe

365 papers A 5B 3C 76Misc 7Journal 149Unranked 125

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Anomalous Behavior Detection in IoT Devices Utilizing Embedded Representations of Power Consumption Waveforms. IEEE Access Ryusei Eda, Nozomu Togawa
2026	C	`conf`	Bit-Width Reduction for Ising Models Proving the Ground State by Topologically Isomorphic n-Partition. ICCE Shu Tomita, Raio Aoki, Shinnosuke Inaba, Masashi Tawada, Nozomu Togawa
2026	C	`conf`	Constraint-Parameterized Spin-Variable Reduction Method for QAP. ICCE Raio Aoki, Takeru Ota, Tatsuhiko Shirai, Nozomu Togawa
2026	C	`conf`	Content-Path Optimization for TV News Programs. ICCE Shoma Kaji, Risa Kaneko, Yuta Hagio, Masaru Miyazaki, Siya Bao, Nozomu Togawa
2026	C	`conf`	Dynamic Variable Selection for subQUBO Annealing Using Hamming Weight. ICCE Yoshihito Saito, Koki Mita, Nozomu Togawa
2026	C	`conf`	Hardware-Trojan Detection Using GraphGPS. ICCE Sho Yoshimi, Yuka Ikegami, Nozomu Togawa
2026	J	`jnl`	Initial Seeds Generation Based on Communication Logs Using LLM for IoT Device Fuzzing. IEICE Trans. Inf. Syst. Hibiki Nakanishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2026	J	`jnl`	Leveraging Non-Exact QUBO Formulation With Quantum Annealing to Optimize 5G Base Station Power Selection. IEEE Access Chihiro Dogo, Kazuhiro Saito, Masashi Tawada, Nozomu Togawa
2025	—	`conf`	A Correction Method Using Multiple Trained Models for Graph-Learning Based Hardware-Trojan Detection. ICCE-Berlin Sho Yoshimi, Yuka Ikegami, Nozomu Togawa
2025	J	`jnl`	An Ising Machine Approach to the Personalized Course Selection Problem. IEEE Access Takeru Ota, Keisuke Fukada, Nozomu Togawa
2025	C	`conf`	An Ising Machine-Based Hybrid Optimization Method Using Constraint Conversion and Correction. ICCE Kinya Iwata, Masashi Tawada, Nozomu Togawa
2025	C	`conf`	Anomalous IoT Behavior Detection Based on SARIMA Reference Waveform. IOLTS Ryusei Eda, Nozomu Togawa
2025	—	`conf`	Anomalous IoT Behavior Detection Utilizing Time-Series Embedded Representation. ICCE-Berlin Ryusei Eda, Nozomu Togawa
2025	C	`conf`	Anomalous IoT Behavior Detection by LSTM-Based Power Waveform Prediction. IoTBDS Ryusei Eda, Nozomu Togawa
2025	—	`conf`	Automated Security Compliance Evaluation Using Hierarchical RAG for IoT Devices with Large-Scale Documentation. IOTSMS Yuka Ikegami, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Automated Test Input Generation Based on Web User Interfaces via Large Language Models. IoTBDS Kento Hasegawa, Hibiki Nakanishi, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Automating the Assessment of Japanese Cyber-Security Technical Assessment Requirements Using Large Language Models. IoTBDS Kento Hasegawa, Yuka Ikegami, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Autonomous Hardware-Trojan Generation Method Using Reinforcement Learning for Random Forest-Based Hardware-Trojan Detection. ICCE Yuka Ikegami, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa
2025	—	`conf`	Contextual Anomalous Behavior Detection in IoT Devices from Power Consumption Using LLM. IOTSMS Ryusei Eda, Hibiki Nakanishi, Nozomu Togawa
2025	—	`conf`	Course Selection Optimization using pVSQA on Quantum Computers. ICCE-Berlin Takeru Ota, Tatsuhiko Shirai, Nozomu Togawa
2025	—	`conf`	Enriching Experiences Through Shared Moments: Travel Recommendation for Heterogeneous Users Using Ising Machines. VTC2025-Spring Siya Bao, Nozomu Togawa
2025	C	`conf`	Evaluation of Hardware-Trojan Detection by Ensemble Learning Model for Circuits Inserted with a Trojan by an Automated Framework. ICCE Sho Yoshimi, Yuka Ikegami, Ryotaro Negishi, Kota Hisafuru, Nozomu Togawa
2025	J	`jnl`	Gen-Power2: Improved Anomaly Detection in IoT Devices Utilizing Generated Power Waveforms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryusei Eda, Kota Hisafuru, Nozomu Togawa
2025	J	`jnl`	Hybrid Iterative Annealing Method Using a Quantum Annealer and a Classical Computer and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Keisuke Fukada, Tatsuhiko Shirai, Nozomu Togawa
2025	J	`jnl`	Hybrid subQUBO Annealing With a Correction Process for Multi-Day Intermodal Trip Planning. IEEE Access Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa
2025	—	`conf`	LLM-Based IoT Fuzzing with Format Consistency and Vulnerability-Aware Test Case Generation. IOTSMS Hibiki Nakanishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	—	`conf`	LLM-Guided Initial Seed Selection for Black-Box IoT Fuzzing to Enhance Vulnerability Detection. ComComAP Hibiki Nakanishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	—	`conf`	LLM-based Fuzzing Method Using UI-based Input Value Generation for IoT Devices. ICCE-Berlin Hibiki Nakanishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa
2025	J	`jnl`	Linearizing Binary Optimization Problems Using Variable Posets for Ising Machines. IEEE Trans. Emerg. Top. Comput. Kentaro Ohno, Nozomu Togawa
2025	C	`conf`	Machine Learning-Based Estimation of Dynamic Travel Times between Points of Interest. ICCE Shoma Kaji, Dai Kajimoto, Tatsuya Noguchi, Toshinori Takayama, Siya Bao, Nozomu Togawa
2025	J	`jnl`	Node-Wise Hardware Trojan Detection Based on Graph Learning. IEEE Trans. Computers Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Performance Comparison of the LLM Models on LLM-Based Seed Generation Method for IoT Device Fuzzing. ICCE Hibiki Nakanishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Personalized Course Selection Optimization Using QAOA. ICCE Takeru Ota, Keisuke Fukada, Tatsuhiko Shirai, Nozomu Togawa
2025	—	`conf`	Predicting Dynamic Travel Time Between Points of Interest Using Machine Learning Models. ICCE-Berlin Shoma Kaji, Toshinori Takayama, Siya Bao, Nozomu Togawa
2025	J	`jnl`	Prioritizing Vulnerability Assessment Items for IoT Devices Based on Suitability Evaluation Using LLMs. IEICE Trans. Inf. Syst. Yuka Ikegami, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Searching Candidate Sequences for RNA Aptamers Using Quantum Computation. ICCE Sora Tomita, Tatsuhiko Shirai, Michiaki Hamada, Tatsuo Adachi, Nozomu Togawa
2025	—	`conf`	Security Conformance Scoring for IoT Devices Through Documentation Analysis Using Large Language Models. ICCE-Berlin Yuka Ikegami, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2025	C	`conf`	Shoe-Based PDR System for Two-Dimensional Tracking. ICCE Dai Kajimoto, Yusuke Tanaka, Siya Bao, Nozomu Togawa
2025	C	`conf`	Solving Task-Select Problems Using a Quantum Annealer. ICCE Koki Mita, Yuta Yachi, Keisuke Fukada, Nozomu Togawa
2025	C	`conf`	SubQUBO Annealing Based on Efficient Binary Variable Selection for Combinatorial Optimization Problems with One-Hot Constraints. ICCE Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa
2025	C	`conf`	Verification of Internal Memory Readout by Voltage Fault Attack on Automotive ECUs. ICCE Ryusei Eda, Kota Hisafuru, Katsuhiko Sato, Yuya Adachi, Nozomu Togawa
2024	J	`jnl`	A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura
2024	—	`conf`	A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting. MWSCAS Yuta Atobe, Masashi Tawada, Nozomu Togawa
2024	J	`jnl`	An Anomalous Behavior Detection Method Utilizing IoT Power Waveform Shapes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kota Hisafuru, Kazunari Takasaki, Nozomu Togawa
2024	C	`conf`	An Interaction Coefficient Control Method for Setting Initial Solutions to Ising Machines. ICCE Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa
2024	J	`jnl`	An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. IEEE Trans. Consumer Electron. Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2024	C	`conf`	Anomalous IoT Behavior Detection by Generated Power Waveforms with Hyper-parameter Tuning. IOLTS Ryusei Eda, Kota Hisafuru, Nozomu Togawa
2024	C	`conf`	Carrying-Mode-Free Stair Ascent and Descent Estimation using Smartphones. ICCE Dai Kajimoto, Etsushi Saeki, Siya Bao, Nozomu Togawa
2024	C	`conf`	Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists. ICCE Ryotaro Negishi, Nozomu Togawa
2024	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa
2024	C	`conf`	Gen-Power: Anomaly Detection in IoT Devices Utilizing Generated Power Waveforms. ICCE Kota Hisafuru, Nozomu Togawa
2024	J	`jnl`	Giving a Quasi-Initial Solution to Ising Machines by Controlling External Magnetic Field Coefficients. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa
2024	J	`jnl`	Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa
2024	C	`conf`	Hybrid Iterative Annealing Method Using a Quantum Annealer and a Classical Computer. ICCE Keisuke Fukada, Tatshuhiko Shirai, Nozomu Togawa
2024	—	`conf`	Initial Seeds Generation Using LLM for IoT Device Fuzzing. IOTSMS Hibiki Nakanishi, Kota Hisafuru, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2024	J	`jnl`	Ising Machine Approach to the Lecturer-Student Assignment Problem. IEEE Access Sora Tomita, Tatsuhiko Shirai, Nozomu Togawa
2024	J	`jnl`	Ising-Machine-Based Solver for Constrained Graph Coloring Problems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Soma Kawakami, Yosuke Mukasa, Siya Bao, Dema Ba, Junya Arai, Satoshi Yagi, Junji Teramoto, Nozomu Togawa
2024	Misc	`conf`	Large-Sized VQE Performance Profiling in Quantum Chemistry Using a Multi-Node Quantum Simulator. QCE Keisuke Fukada, Tatsuhiko Shirai, Mikio Morita, Yoshinori Tomita, Koichi Kimura, Nozomu Togawa
2024	Misc	`conf`	Multi-Day Intermodal Trip Planning Using subQUBO Annealing with Correction Processing. QCE Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa
2024	Misc	`conf`	Non-zero Coefficients Removing Method to Improve the Ising Machine Solving Performance. QCE Kinya Iwata, Masashi Tawada, Nozomu Togawa
2024	Misc	`conf`	Optimization of Base Station Power Supply Selection by Quantum Annealing. QCE Chihiro Dogo, Kazuhiro Saito, Nozomu Togawa
2024	C	`conf`	Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. ICCE Yui Tsuyumine, Kenichi Masuda, Takeshi Hachikawa, Tsuyoshi Haga, Yuta Yachi, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
2024	Misc	`conf`	Personalized Course Selection Optimization Using an Ising Machine. QCE Takeru Ota, Keisuke Fukada, Nozomu Togawa
2024	—	`conf`	Prioritizing Vulnerability Assessment Items Using LLM Based on IoT Device Documentations. IOTSMS Yuka Ikegami, Ryotaro Negishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2024	Misc	`conf`	QUBO Coefficient Dynamic Ratio Shrinking Method for Quantum Annealers. QCE Yuta Yachi, Masashi Tawada, Nozomu Togawa
2024	J	`jnl`	QUBO Formulation Using Sequence Pair With Search Space Restriction for Rectangle Packing Problem. IEEE Access Akihisa Okada, Keisuke Otaki, Tadayoshi Matsumori, Hiroaki Yoshida, Kotaro Terada, Nozomu Togawa
2024	C	`conf`	Time-Dependent Multi-Objective Trip Planning by Ant Colony Optimization with Route API. ICCE Etsushi Saeki, Siya Bao, Toshinori Takayama, Nozomu Togawa
2024	J	`jnl`	Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem. IEEE Access Kentaro Ohno, Tatsuhiko Shirai, Nozomu Togawa
2024	J	`jnl`	Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem. CoRR Kentaro Ohno, Tatsuhiko Shirai, Nozomu Togawa
2024	Misc	`conf`	Variable Reduction Method for Quadratic Three-Dimensional Assignment Problem with FMQA. QCE Sora Tomita, Tatsuhiko Shirai, Nozomu Togawa
2023	—	`conf`	A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. SOCC Yuta Yachi, Masashi Tawada, Nozomu Togawa
2023	C	`conf`	A Constrained Graph Coloring Solver Based on Ising Machines. ICCE Soma Kawakami, Yosuke Mukasa, Siya Bao, Dema Ba, Junya Arai, Satoshi Yagi, Junji Teramoto, Nozomu Togawa
2023	C	`conf`	A Quasi-Initial Solution Giving Method for Ising Machines by Controlling External Magnetic Field Coefficients. ICCE Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa
2023	J	`jnl`	An Efficient Combined Bit-Width Reducing Method for Ising Models. IEICE Trans. Inf. Syst. Yuta Yachi, Masashi Tawada, Nozomu Togawa
2023	J	`jnl`	Dynamical Process of a Bit-Width Reduced Ising Model With Simulated Annealing. IEEE Access Shuta Kikuchi, Nozomu Togawa, Shu Tanaka
2023	C	`conf`	Fast Hyperparameter Tuning for Ising Machines. ICCE Matthieu Parizy, Norihiro Kakuko, Nozomu Togawa
2023	C	`conf`	Fast and Accurate Smartglass Angles Inference Based on Periodic Behavior in Walking. ICCE Dai Sato, Nozomu Togawa
2023	J	`jnl`	Linearization via Ordering Variables in Binary Optimization for Ising Machines. CoRR Kentaro Ohno, Nozomu Togawa
2023	B	`conf`	Membership Inference Attacks against GNN-based Hardware Trojan Detection. TrustCom Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2023	—	`conf`	Multi-Day Intermodal Travel Planning for Urban Cities Using Ising Machines. ITSC Siya Bao, Nozomu Togawa
2023	J	`jnl`	Multi-Spin-Flip Engineering in an Ising Machine. IEEE Trans. Computers Tatsuhiko Shirai, Nozomu Togawa
2023	J	`jnl`	QuDASH: Quantum-Inspired Rate Adaptation Approach for DASH Video Streaming. IEEE Access Bo Wei, Hang Song, Makoto Nakamura, Koichi Kimura, Nozomu Togawa, Jiro Katto
2023	J	`jnl`	R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training. IEEE Trans. Computers Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa
2023	J	`jnl`	Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines. IEEE Trans. Computers Tatsuhiko Shirai, Nozomu Togawa
2023	J	`jnl`	Trip Planning Based on subQUBO Annealing. IEEE Access Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa
2022	C	`conf`	A PDR Method Using Smartglasses Reducing Accumulated Errors by Detecting User's Stop Motions. ICCE Dai Sato, Nozomu Togawa
2022	C	`conf`	An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes. IOLTS Kota Hisafuru, Kazunari Takasaki, Nozomu Togawa
2022	—	`conf`	Autonomous driving system with feature extraction using a binarized autoencoder. FPT Kota Hisafuru, Ryotaro Negishi, Soma Kawakami, Dai Sato, Kazuki Yamashita, Keisuke Fukada, Nozomu Togawa
2022	—	`conf`	Cardinality Constrained Portfolio Optimization on an Ising Machine. SOCC Matthieu Parizy, Przemyslaw Sadowski, Nozomu Togawa
2022	J	`jnl`	Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations. J. Inf. Process. Tomoya Wakaizumi, Nozomu Togawa
2022	C	`conf`	Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. IOLTS Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa
2022	C	`conf`	Efficient Coefficient Bit-Width Reduction Method for Ising Machines. ICCE Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa
2022	J	`jnl`	Fast Hyperparameter Tuning for Ising Machines. CoRR Matthieu Parizy, Norihiro Kakuko, Nozomu Togawa
2022	J	`jnl`	Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuki Kurihara, Nozomu Togawa
2022	—	`conf`	Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models. ICCE-Berlin Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa
2022	J	`jnl`	How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2022	J	`jnl`	Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. IEEE Trans. Computers Yuta Atobe, Masashi Tawada, Nozomu Togawa
2022	J	`jnl`	Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records. IEEE Access Etsushi Saeki, Siya Bao, Toshinori Takayama, Nozomu Togawa
2022	C	`conf`	QUBO Matrix Distorting Method for Consumer Applications. ICCE Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
2022	J	`jnl`	QuDASH: Quantum-inspired rate adaptation approach for DASH video streaming. CoRR Bo Wei, Hang Song, Makoto Nakamura, Koichi Kimura, Nozomu Togawa, Jiro Katto
2022	J	`jnl`	R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training. CoRR Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa
2021	—	`conf`	A PDR Method Combining Smartphone and Smartwatch based on Multi-Scenario Map Matching. GCCE Tomoya Wakaizumi, Nozomu Togawa
2021	J	`jnl`	A Route Recommendation Method Considering Individual User's Preferences by Monte-Carlo Tree Search and Its Evaluations. J. Inf. Process. Yuta Ishizaki, Yurie Koyama, Toshinori Takayama, Nozomu Togawa
2021	J	`jnl`	A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine. IEEE Access Keisuke Fukada, Matthieu Parizy, Yoshinori Tomita, Nozomu Togawa
2021	J	`jnl`	A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Tomotaka Inoue, Nozomu Togawa
2021	C	`conf`	An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM. IOLTS Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa
2021	J	`jnl`	An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa
2021	—	`conf`	An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. VLSI-DAT Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2021	C	`conf`	An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes. ICCE Tomoya Wakaizumi, Nozomu Togawa
2021	J	`jnl`	An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks. IEICE Trans. Inf. Syst. Yosuke Mukasa, Tomoya Wakaizumi, Shu Tanaka, Nozomu Togawa
2021	—	`conf`	An autonomous driving system utilizing image processing accelerated by FPGA. FPT Kazunari Takasaki, Kota Hisafuru, Ryotaro Negishi, Kazuki Yamashita, Keisuke Fukada, Tomoya Wakaizumi, Nozomu Togawa
2021	J	`jnl`	Analysis and Acceleration of the Quadratic Knapsack Problem on an Ising Machine. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Matthieu Parizy, Nozomu Togawa
2021	C	`conf`	Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. IOLTS Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa
2021	J	`jnl`	Experimental Evaluations of Parallel Tempering on an Ising Machine. IPSJ Trans. Syst. LSI Des. Methodol. Yosuke Mukasa, Shu Tanaka, Nozomu Togawa
2021	J	`jnl`	Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. J. Inf. Process. Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa
2021	C	`conf`	Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests. IOLTS Tatsuki Kurihara, Nozomu Togawa
2021	J	`jnl`	Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. IEICE Trans. Inf. Syst. Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
2021	—	`conf`	Multi-day Travel Planning Using Ising Machines for Real-world Applications. ITSC Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
2021	J	`jnl`	Node-wise Hardware Trojan Detection Based on Graph Learning. CoRR Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa
2021	J	`jnl`	Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine. IEEE Access Kensuke Tamura, Tatsuhiko Shirai, Hosho Katsura, Shu Tanaka, Nozomu Togawa
2021	C	`conf`	Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ICCE Shota Matsuno, Masashi Tawada, Nozomu Togawa
2021	J	`jnl`	Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations. IEICE Trans. Inf. Syst. Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Nozomu Togawa
2021	B	`conf`	Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training. CANS Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Nozomu Togawa
2021	C	`conf`	Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine. ICCE Yosuke Mukasa, Tomoya Wakaizumi, Shu Tanaka, Nozomu Togawa
2020	J	`jnl`	A Capacitance Measurement Device for Running Hardware Devices and Its Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa
2020	C	`conf`	A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. ICCE Masashi Tawada, Shu Tanaka, Nozomu Togawa
2020	C	`conf`	An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors. IOLTS Kazunari Takasaki, Kento Hasegawa, Ryoichi Kida, Nozomu Togawa
2020	—	`conf`	Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. NEWCAS Masashi Tawada, Nozomu Togawa
2020	—	`conf`	Document-Level Sentiment Classification in Japanese by Stem-Based Segmentation with Category and Data-Source Information. ICSC Siya Bao, Nozomu Togawa
2020	C	`conf`	Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods. IOLTS Tatsuki Kurihara, Kento Hasegawa, Nozomu Togawa
2020	—	`conf`	FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
2020	J	`jnl`	Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines. IEEE Access Tatsuhiko Shirai, Shu Tanaka, Nozomu Togawa
2020	—	`conf`	Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020	J	`jnl`	Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2020	—	`conf`	Theory of Ising Machines and a Common Software Platform for Ising Machines. ASP-DAC Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa
2020	J	`jnl`	Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. IEICE Trans. Inf. Syst. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2019	J	`jnl`	A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa
2019	—	`conf`	A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines. ICCE-Berlin Kota Takehara, Daisuke Oku, Yoshiki Matsuda, Shu Tanaka, Nozomu Togawa
2019	J	`jnl`	A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	J	`jnl`	A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	A Route Recommendation Method Based on Personal Preferences by Monte-Carlo Tree Search. ICCE-Berlin Yuta Ishizaki, Toshinori Takayama, Nozomu Togawa
2019	—	`conf`	A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. ICIS (best papers) Siya Bao, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa
2019	J	`jnl`	An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2019	J	`jnl`	Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. MWSCAS Yuta Ideguchi, Norifumi Kamiya, Masashi Tawada, Nozomu Togawa
2019	—	`conf`	Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. ICCE-Berlin Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
2019	C	`conf`	Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2019	C	`conf`	Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis. IOLTS Kento Hasegawa, Kiyoshi Chikamatsu, Nozomu Togawa
2019	C	`conf`	Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2019	—	`conf`	Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. FPT Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa
2019	—	`conf`	Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine. ICCE-Berlin Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Hidetoshi Matsuoka, Kaoru Kawamura, Nozomu Togawa
2019	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Nozomu Togawa
2019	C	`conf`	Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. ICCE-Berlin Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. ISCAS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	A hardware-Trojan classification method utilizing boundary net structures. ICCE Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	An Ising model mapping to solve rectangle packing problem. VLSI-DAT Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Bicycle Behavior Recognition using Sensors Equipped with Smartphone. ICCE-Berlin Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection. APCCAS Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa
2018	—	`conf`	Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. ICCE-Berlin Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa
2018	C	`conf`	Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. IOLTS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2018	—	`conf`	Hardware Trojan Detection Utilizing Machine Learning Approaches. TrustCom/BigDataSE Kento Hasegawa, Youhua Shi, Nozomu Togawa
2018	J	`jnl`	Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. IEEE BigData Siya Bao, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Nozomu Togawa
2018	C	`conf`	Road-illuminance level inference across road networks based on Bayesian analysis. ICCE Siya Bao, Masao Yanagisawa, Nozomu Togawa
2018	—	`conf`	Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. ICCE-Berlin Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2018	J	`jnl`	Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2017	—	`conf`	A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A selector-based FFT processor and its FPGA implementation. ISOCC Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	A stayed location estimation method for sparse GPS positioning information. GCCE Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. GCCE Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Designing hardware trojans and their detection based on a SVM-based approach. ASICON Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Effective write-reduction method for MLC non-volatile memory. ISCAS Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. ASICON Daiki Asai, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Hardware Trojan detection and classification based on steady state learning. IOLTS Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Hardware Trojans classification for gate-level netlists using multi-layer neural networks. IOLTS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Nozomu Togawa
2017	—	`conf`	Personalized one-day travel with multi-nearby-landmark recommendation. ICCE-Berlin Siya Bao, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Robust AES circuit design for delay variation using suspicious timing error prediction. ISOCC Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa
2017	—	`conf`	Soft error tolerant latch designs with low power consumption (invited paper). ASICON Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
2017	J	`jnl`	Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2017	C	`conf`	Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ISCAS Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A high-performance circuit design algorithm using data dependent approximation. ISOCC Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	A safe and comprehensive route finding method for pedestrian based on lighting and landmark. GCCE Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. GCCE Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Hardware Trojans classification for gate-level netlists based on machine learning. IOLTS Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Hash-table and balanced-tree based FIB architecture for CCN routers. ISOCC Kenta Shimazaki, Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki, Toshitaka Tsuda, Nozomu Togawa
2016	—	`conf`	Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016	J	`jnl`	Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. Nozomu Togawa
2016	J	`jnl`	Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. IEICE Electron. Express Koki Igawa, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Pedestrian navigation based on landmark recognition using glass-type wearable devices. GCCE Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Redesign for untrusted gate-level netlists. IOLTS Masaru Oya, Masao Yanagisawa, Nozomu Togawa
2016	—	`conf`	Rotator-based multiplexer network synthesis for field-data extractors. SoCC Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016	C	`conf`	Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. ISCAS Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	C	`conf`	A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ISCAS Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A landmark-based route recommendation method for pedestrian walking strategies. GCCE Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A low-power soft error tolerant latch scheme. ASICON Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2015	—	`conf`	A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	A visible corner-landmark based route finding algorithm for pedestrian navigation. GCCE Kengo Takeda, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2015	A	`conf`	Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
2015	B	`conf`	Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization. GLOBECOM Kou Kikuta, Eiji Oki, Naoaki Yamanaka, Nozomu Togawa, Hidenori Nakazato
2015	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. ASICON Keita Igarashi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Partitioning-based multiplexer network synthesis for field-data extractors. SoCC Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2015	J	`jnl`	Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2015	—	`conf`	Small-sized and noise-reducing power analyzer design for low-power IoT devices. ASICON Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. Inf. Media Technol. Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Yuta Hagio, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. APCCAS Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	In-situ timing monitoring methods for variation-resilient designs. APCCAS Youhua Shi, Nozomu Togawa
2014	C	`conf`	Linear and bi-linear interpolation circuits using selector logics and their evaluations. ISCAS Masashi Shio, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	J	`jnl`	Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	C	`conf`	Scan-based attack on the LED block cipher using scan signatures. ISCAS Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Scan-based side-channel attack on Camellia cipher using scan signatures. APCCAS Huiqian Hang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Secure scan design using improved random order and its evaluations. APCCAS Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2014	—	`conf`	Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. ISCAS Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
2013	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Inf. Media Technol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. Inf. Media Technol. Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2013	J	`jnl`	Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. J. Inf. Process. Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Scan-based attack against Trivium stream cipher independent of scan structure. ASICON Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa
2013	C	`conf`	Secure Scan Design with Dynamically Configurable Connection. PRDC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2013	—	`conf`	Suspicious timing error prediction with in-cycle clock gating. ISQED Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa
2012	J	`jnl`	A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. IPSJ Trans. Syst. LSI Des. Methodol. Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Seungju Lee, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	A hybrid NoC architecture utilizing packet transmission priority control method. APCCAS Seungju Lee, Nozomu Togawa, Yusuke Sekihara, Takashi Aoki, Akira Onozawa
2012	C	`conf`	A novel BMNoC configuration algorithm utilizing communication volume and locality among cores. ISCAS Seungju Lee, Nozomu Togawa, Takashi Aoki, Akira Onozawa
2012	C	`conf`	An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures. Inf. Media Technol. Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Energy-efficient high-level synthesis for HDR architectures with clock gating. ISOCC Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	MH IEICE Electron. Express Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	J	`jnl`	Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2012	J	`jnl`	Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa
2012	—	`conf`	Scan-based attack against DES cryptosystems using scan signatures. APCCAS Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
2012	—	`conf`	Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. APCCAS Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa
2011	J	`jnl`	A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2011	J	`jnl`	Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
2011	J	`jnl`	Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto
2011	J	`jnl`	Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2011	J	`jnl`	Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2010	—	`conf`	A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	—	`conf`	BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	J	`jnl`	Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	C	`conf`	Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	J	`jnl`	Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
2010	—	`conf`	Scan-based attack against elliptic curve cryptosystems. ASP-DAC Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	C	`conf`	State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2010	—	`conf`	VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	A	`conf`	Design-for-secure-test for crypto cores. ITC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	—	`conf`	Exact and fast L1 cache simulation for embedded systems. ASP-DAC Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2009	J	`jnl`	X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh
2008	J	`jnl`	Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	GECOM: Test data compression combined with all unknown response masking. ASP-DAC Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	J	`jnl`	Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2008	—	`conf`	Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2 ASP-DAC Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2008	—	`conf`	Unknown response masking with minimized observable response loss and mask data. APCCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007	C	`conf`	Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2007	A	`conf`	Power-efficient LDPC code decoder architecture. ISLPED Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2006	J	`jnl`	A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	C	`conf`	A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2006	—	`conf`	An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2006	—	`conf`	Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2006	J	`jnl`	Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2006	J	`jnl`	Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2006	J	`jnl`	Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
2005	J	`jnl`	A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	A processor core synthesis system in IP-based SoC design. ASP-DAC Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
2005	C	`conf`	Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa
2005	J	`jnl`	Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Trans. Inf. Syst. Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2005	—	`conf`	Reconfigurable adaptive FEC system with interleaving. ASP-DAC Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto
2005	J	`jnl`	Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2005	—	`conf`	Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	A thread partitioning algorithm in low power high-level synthesis. ASP-DAC Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2004	—	`conf`	Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki
2003	J	`jnl`	A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2003	—	`conf`	A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	—	`conf`	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	J	`jnl`	High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2002	—	`conf`	VLSI Architecture for a Flexible Motion Estimation with Parameters. ASP-DAC/VLSI Design Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2001	—	`conf`	Area/delay estimation for digital signal processor cores. ASP-DAC Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
2000	—	`conf`	An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki
1999	—	`conf`	A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki
1999	J	`jnl`	A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki
1998	—	`conf`	A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
1998	—	`conf`	An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki
1998	J	`jnl`	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
1997	J	`jnl`	A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. J. Circuits Syst. Comput. Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1997	—	`conf`	A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1995	—	`conf`	Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1994	C	`conf`	A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1994	A	`conf`	A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki