Noureddine Chabini

43 papers C 4Misc 2Journal 16Unranked 21

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	LUT-Based Multipliers for IEEE-754 Floating Point Arithmetic on FPGAs. UEMCON Noureddine Chabini, Marilyn Claire Wolf, Rachid Beguenane
2023	J	`jnl`	An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method. IEEE Access Samir Dahmani, Mountassar Maamoun, Ghania Zerari, Noureddine Chabini, Rachid Beguenane
2023	—	`conf`	Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter. CCECE Justin Woelfle, Noureddine Chabini, Rachid Beguenane
2023	—	`conf`	FPGA-Based 8x8 Bits Signed Multipliers Using LUTs. CCECE Noureddine Chabini, Rachid Beguenane
2023	—	`conf`	FPGA-Based Digital FIR Filters With Small Coefficients and Large Data Input. CCWC Noureddine Chabini, Rachid Beguenane
2023	—	`conf`	Path Balancing for Reducing Dynamic Power Consumption in Digital Designs Containing IP-Blocks. AIIoT Noureddine Chabini, Marilyn Claire Wolf
2022	—	`conf`	An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs. ICECOCS Noureddine Chabini, Said Belkouch, Mohamed Najoui
2022	—	`conf`	FPGA-Based Designs of the Factorial Function. CCECE Noureddine Chabini, Rachid Beguenane
2022	J	`jnl`	Ultra-fast and efficient implementation schemes of complex matrix multiplication algorithm for VLIW architectures. Comput. Electr. Eng. Mohamed Najoui, Mounir Bahtat, Abdessamad Klilou, Anas Hatim, Said Belkouch, Atman Jbari, Noureddine Chabini
2021	J	`jnl`	Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization. IET Circuits Devices Syst. Mountassar Maamoun, Adnane Hassani, Samir Dahmani, Hocine Ait Saadi, Ghania Zerari, Noureddine Chabini, Rachid Beguenane
2020	J	`jnl`	Novel Implementation Approach with Enhanced Memory Access Performance of MGS Algorithm for VLIW Architecture. J. Circuits Syst. Comput. Mohamed Najoui, Anas Hatim, Said Belkouch, Noureddine Chabini
2017	—	`conf`	Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2017	J	`jnl`	Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini
2017	J	`jnl`	VLIW DSP-Based Low-Level Instruction Scheme of Givens QR Decomposition for Real-Time Processing. J. Circuits Syst. Comput. Mohamed Najoui, Mounir Bahtat, Anas Hatim, Said Belkouch, Noureddine Chabini
2015	C	`conf`	Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. AICCSA Noureddine Chabini, Said Belkouch
2015	—	`conf`	Reducing the number of embedded multipliers in squaring large size complex numbers. ICM Fatima-Ezzahra Guessous, Noureddine Chabini
2013	J	`jnl`	Design optimization of the quantization and a pipelined 2D-DCT for real-time applications. Multim. Tools Appl. Anas Hatim, Said Belkouch, Mohamed El Aakif, Moha M'rabet Hassani, Noureddine Chabini
2012	—	`conf`	An improved BCD adder using 6-LUT FPGAs. NEWCAS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2012	J	`jnl`	Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois
2011	—	`conf`	Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2011	—	`conf`	Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2011	J	`jnl`	Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus. IET Comput. Digit. Tech. Noureddine Chabini, Marilyn Wolf
2010	J	`jnl`	FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2009	J	`jnl`	Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfigurable Comput. Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2009	—	`conf`	Two level decomposition based matrix multiplication for FPGAs. ICECS Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini
2007	—	`conf`	A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs. PATMOS Noureddine Chabini
2007	—	`conf`	An approach for computing the initial state for retimed synchronous sequential circuits. HLDVT Noureddine Chabini, Wayne H. Wolf
2007	—	`conf`	FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2007	J	`jnl`	Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2007	—	`conf`	Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints. IESS Noureddine Chabini, Wayne H. Wolf
2007	C	`conf`	Register binding guided by the size of variables. ICCD Noureddine Chabini, Wayne H. Wolf
2006	C	`conf`	An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois
2006	—	`conf`	Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois
2005	J	`jnl`	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria
2005	J	`jnl`	Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints. IEEE Trans. Very Large Scale Integr. Syst. Noureddine Chabini, Wayne H. Wolf
2004	Misc	`conf`	An approach for integrating basic retiming and software pipelining. EMSOFT Noureddine Chabini, Wayne H. Wolf
2004	—	`conf`	An approach for reducing dynamic power consumption in synchronous sequential digital designs. ASP-DAC Noureddine Chabini, Wayne H. Wolf
2004	J	`jnl`	Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling. IEEE Trans. Very Large Scale Integr. Syst. Noureddine Chabini, Wayne H. Wolf
2003	J	`jnl`	Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
2003	Misc	`conf`	Minimizing Variables' Lifetime in Loop-Intensive Applications. EMSOFT Noureddine Chabini, Wayne H. Wolf
2003	—	`conf`	Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. ACM Great Lakes Symposium on VLSI Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria
2001	C	`conf`	Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. ICCD Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
2001	—	`conf`	Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques. ISSS Noureddine Chabini, Yvon Savaria