Norman P. Jouppi

143 papers A* 50A 21B 4C 1Misc 2Journal 48Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Ironwood: Delivering Best in Class perf, perf/TCO and perf/Watt for Reasoning Model Training and Serving. HCS Norman P. Jouppi, Sridhar Lakshmanamurthy
2024	—	`conf`	FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. AutoML Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li
2023	—	`conf`	A Machine Learning Supercomputer with an Optically Reconfigurable Interconnect and Embeddings Support. HCS Norman P. Jouppi, Andy Swing
2023	J	`jnl`	Corona: System Implications of Emerging Nanophotonic Technology. CoRR Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2023	J	`jnl`	FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. CoRR Jordan Dotzel, Gang Wu, Andrew Li, Muhammad Umar, Yun Ni, Mohamed S. Abdelfattah, Zhiru Zhang, Liqun Cheng, Martin G. Dixon, Norman P. Jouppi, Quoc V. Le, Sheng Li
2023	—	`conf`	Hyperscale Hardware Optimized Neural Architecture Search. ASPLOS (3) Sheng Li, Garrett Andersen, Tao Chen, Liqun Cheng, Julian Grady, Da Huang, Quoc V. Le, Andrew Li, Xin Li, Yang Li, Chen Liang, Yifeng Lu, Yun Ni, Ruoming Pang, Mingxing Tan, Martin Wicke, Gang Wu, Shengqi Zhu, Parthasarathy Ranganathan, Norman P. Jouppi
2023	J	`jnl`	RETROSPECTIVE: Corona: System Implications of Emerging Nanophotonic Technology. CoRR Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2023	A*	`conf`	TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. ISCA Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson
2023	J	`jnl`	TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. CoRR Norman P. Jouppi, George Kurian, Sheng Li, Peter C. Ma, Rahul Nagarajan, Lifeng Nai, Nishant Patil, Suvinay Subramanian, Andy Swing, Brian Towles, Cliff Young, Xiang Zhou, Zongwei Zhou, David A. Patterson
2021	A*	`conf`	NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. HPCA Tianqi Tang, Sheng Li, Lifeng Nai, Norman P. Jouppi, Yuan Xie
2021	A*	`conf`	Searching for Fast Model Families on Datacenter Accelerators. CVPR Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi
2021	J	`jnl`	Searching for Fast Model Families on Datacenter Accelerators. CoRR Sheng Li, Mingxing Tan, Ruoming Pang, Andrew Li, Liqun Cheng, Quoc V. Le, Norman P. Jouppi
2021	A*	`conf`	Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product. ISCA Norman P. Jouppi, Doe Hyun Yoon, Matthew Ashcraft, Mark Gottscho, Thomas B. Jablin, George Kurian, James Laudon, Sheng Li, Peter C. Ma, Xiaoyu Ma, Thomas Norrie, Nishant Patil, Sushma Prasad, Cliff Young, Zongwei Zhou, David A. Patterson
2021	J	`jnl`	The Design Process for Google's Training Chips: TPUv2 and TPUv3. IEEE Micro Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson
2020	J	`jnl`	A domain-specific supercomputer for training deep neural networks. Commun. ACM Norman P. Jouppi, Doe Hyun Yoon, George Kurian, Sheng Li, Nishant Patil, James Laudon, Cliff Young, David A. Patterson
2020	—	`conf`	Google's Training Chips Revealed: TPUv2 and TPUv3. Hot Chips Symposium Thomas Norrie, Nishant Patil, Doe Hyun Yoon, George Kurian, Sheng Li, James Laudon, Cliff Young, Norman P. Jouppi, David A. Patterson
2018	J	`jnl`	A domain-specific architecture for deep neural networks. Commun. ACM Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson
2018	J	`jnl`	Motivation for and Evaluation of the First Tensor Processing Unit. IEEE Micro Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson
2017	A*	`conf`	In-Datacenter Performance Analysis of a Tensor Processing Unit. ISCA Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon
2017	J	`jnl`	In-Datacenter Performance Analysis of a Tensor Processing Unit. CoRR Norman P. Jouppi, Cliff Young, Nishant Patil, David A. Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, Doe Hyun Yoon
2016	J	`jnl`	Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
2015	J	`jnl`	CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2015	A	`conf`	History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
2014	J	`jnl`	Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. ACM Trans. Archit. Code Optim. HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu
2014	J	`jnl`	Endurance-aware cache line management for non-volatile caches. ACM Trans. Archit. Code Optim. Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2013	B	`conf`	A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies. ISPASS Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013	J	`jnl`	A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. ACM Trans. Archit. Code Optim. Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2013	A	`conf`	Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013	A*	`conf`	Kiln: closing the performance gap between systems with and without persistence support. MICRO Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi
2013	B	`conf`	McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. ISPASS Jung Ho Ahn, Sheng Li, Seongil O, Norman P. Jouppi
2013	A	`conf`	Practical nonvolatile multilevel-cell phase change memory. SC Doe Hyun Yoon, Jichuan Chang, Robert S. Schreiber, Norman P. Jouppi
2013	J	`jnl`	The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. ACM Trans. Archit. Code Optim. Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
2013	A*	`conf`	Understanding the trade-offs in multi-level cell ReRAM memory design. DAC Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013	A*	`conf`	i HPCA Jue Wang, Xiangyu Dong, Yuan Xie, Norman P. Jouppi
2012	A	`conf`	CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi
2012	A	`conf`	CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
2012	A	`conf`	Design trade-offs for high density cross-point resistive memory. ISLPED Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012	J	`jnl`	Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
2012	J	`jnl`	Improving System Energy Efficiency with Memory Rank Subsetting. ACM Trans. Archit. Code Optim. Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber
2012	A*	`conf`	LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2012	A	`conf`	MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. SC Sheng Li, Doe Hyun Yoon, Ke Chen, Jishen Zhao, Jung Ho Ahn, Jay B. Brockman, Yuan Xie, Norman P. Jouppi
2012	J	`jnl`	NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiangyu Dong, Cong Xu, Yuan Xie, Norman P. Jouppi
2012	J	`jnl`	Optical High Radix Switch Design. IEEE Micro Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2012	A*	`conf`	Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2011	A	`conf`	CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. ICCAD Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi
2011	—	`ch.`	CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Low Power Networks-on-Chip Jung Ho Ahn, Raymond G. Beausoleil, Nathan L. Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Matteo Monchiero, Naveen Muralimanohar, Robert Schreiber, Dana Vantrease
2011	A*	`conf`	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2011	J	`jnl`	DRAM errors in the wild: technical perspective. Commun. ACM Norman P. Jouppi
2011	A	`conf`	Design implications of memristor-based RRAM cross-point structures. DATE Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2011	A*	`conf`	FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
2011	J	`jnl`	Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2011	—	`book`	Multi-Core Cache Hierarchies Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar
2011	A	`conf`	System implications of memory reliability in exascale computing. SC Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi
2011	A*	`conf`	System-level integrated server architectures for scale-out datacenters. MICRO Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi
2011	A*	`conf`	The role of optics in future high radix switch design. ISCA Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
2010	A*	`conf`	Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
2010	A	`conf`	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
2009	J	`jnl`	A High-Speed Optical Multidrop Bus for Computer Interconnections. IEEE Micro Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Huei Pei Kuo, Joseph Straznicky, Norman P. Jouppi, Shih-Yuan Wang
2009	A	`conf`	Emerging technologies and their impact on system design. ISLPED Norman P. Jouppi, Yuan Xie
2009	A	`conf`	Future scaling of processor-memory interfaces. SC Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, Robert S. Schreiber
2009	J	`jnl`	Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2009	A	`conf`	Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie
2009	A*	`conf`	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. MICRO Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
2009	J	`jnl`	Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs. IEEE Comput. Archit. Lett. Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber, Norman P. Jouppi
2009	A	`conf`	PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM. ICCAD Xiangyu Dong, Norman P. Jouppi, Yuan Xie
2009	—	`conf`	Resilience Challenges for Exascale Systems. DFT Norman P. Jouppi
2009	J	`jnl`	Technical perspective - Software and hardware support for deterministic replay of parallel programs. Commun. ACM Norman P. Jouppi
2008	A*	`conf`	A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies. ISCA Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi
2008	—	`conf`	A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Hot Interconnects Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals
2008	—	`conf`	A Nanophotonic Interconnect for High-Performance Many-Core Computation. Hot Interconnects Raymond G. Beausoleil, Jung Ho Ahn, Nathan L. Binkert, Al Davis, David Fattal, Marco Fiorentino, Norman P. Jouppi, Moray McLaren, Charles M. Santori, Robert S. Schreiber, S. M. Spillane, Dana Vantrease, Qianfan Xu
2008	J	`jnl`	Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2008	A*	`conf`	Corona: System Implications of Emerging Nanophotonic Technology. ISCA Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan L. Binkert, Raymond G. Beausoleil, Jung Ho Ahn
2008	A*	`conf`	Implementing high availability memory with a duplication cache. MICRO Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan
2008	J	`jnl`	Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2008	A	`conf`	System implications of integrated photonics. ISLPED Norman P. Jouppi
2007	A*	`conf`	Configurable isolation: building high availability systems with commodity multi-core processors. ISCA Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
2007	A	`conf`	High-performance ethernet-based communications for future multi-core processors. SC Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi
2007	J	`jnl`	Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06). SIGARCH Comput. Archit. News Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi
2007	J	`jnl`	Isolation in Commodity Multicore Processors. Computer Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, James E. Smith
2007	A	`conf`	Microprocessors in the era of terascale integration. DATE Shekhar Borkar, Norman P. Jouppi, Per Stenström
2007	A*	`conf`	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
2006	A	`conf`	Architecture - The potential energy efficiency of vector acceleration. SC Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi
2006	B	`conf`	Core architecture optimization for heterogeneous chip multiprocessors. PACT Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
2006	A*	`conf`	Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder
2006	Misc	`conf`	Improving the performance and power efficiency of shared helpers in CMPs. CASES Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Timothy Sherwood, Suleyman Sair
2005	J	`jnl`	Dynamically configurable shared CMP helper engines for improved performance. SIGARCH Comput. Archit. News Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, Timothy Sherwood
2005	A*	`conf`	Enterprise IT Trends and Implications for Architecture Research. HPCA Parthasarathy Ranganathan, Norman P. Jouppi
2005	J	`jnl`	Fast synchronization for chip multiprocessors. SIGARCH Comput. Archit. News Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker
2005	J	`jnl`	Heterogeneous Chip Multiprocessors. Computer Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan
2005	J	`jnl`	Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2005	B	`conf`	System-wide performance monitors and their application to the optimization of coherent memory accesses. PPoPP Jean-Francois Collard, Norman P. Jouppi, Sami Yehia
2005	A*	`conf`	Telepresence Systems With Automatic Preservation of User Head Height, Local Rotation, and Remote Translation. ICRA Norman P. Jouppi, Stan Thomas
2005	A*	`conf`	The Future Evolution of High-Performance Microprocessors. MICRO Norman P. Jouppi
2004	A*	`conf`	A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking. ICRA Norman P. Jouppi, Subu Iyer, Wayne Mack, April Slayden Mitchell, Stan Thomas
2004	A*	`conf`	BiReality: mutually-immersive telepresence. ACM Multimedia Norman P. Jouppi, Subu Iyer, Stan Thomas, April Slayden
2004	A*	`conf`	Conjoined-Core Chip Multiprocessing. MICRO Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
2004	A	`conf`	Region of interest editing of MPEG-2 video streams in the compressed domain. ICME Jacob Augustine, Shivarama Rao, Norman P. Jouppi, Subu Iyer
2004	A*	`conf`	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
2004	Misc	`conf`	The Future Evolution of High-Performance Microprocessors. HiPC Norman P. Jouppi
2003	J	`jnl`	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. IEEE Comput. Archit. Lett. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
2003	A*	`conf`	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. MICRO Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
2002	A	`conf`	First steps towards mutually-immersive mobile telepresence. CSCW Norman P. Jouppi
2002	—	`conf`	First steps towards mutually-immersive mobile telepresence. CSCW Videos Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, April Slayden
2002	A*	`conf`	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. ISCA M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
2000	—	`conf`	Prefiltered Antialiased Lines Using Half-Plane Distance Functions. Workshop on Graphics Hardware Bob McNamara, Joel McCormack, Norman P. Jouppi
2000	A*	`conf`	Reconfigurable caches and their application to media processing. ISCA Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
1999	A*	`conf`	Feline: Fast Elliptical Lines for Anisotropic Texture Mapping. SIGGRAPH Joel McCormack, Ronald N. Perry, Keith I. Farkas, Norman P. Jouppi
1999	J	`jnl`	Implementing Neon: a 256-bit graphics accelerator. IEEE Micro Joel McCormack, Bob McNamara, Chris Gianos, Norman P. Jouppi, Todd A. Dutton, John H. Zurawski, Larry Seiler, Kenneth W. Correll
1999	A*	`conf`	Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions. ISCA Parthasarathy Ranganathan, Sarita V. Adve, Norman P. Jouppi
1999	J	`jnl`	Real products, real technology Guest Editor's Introduction]. IEEE Micro Norman P. Jouppi, John Wawrzynek
1999	J	`jnl`	The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. Int. J. Parallel Program. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1999	—	`conf`	Z3: An Economical Hardware Technique for High-Quality Antialiasing and Transparency. Workshop on Graphics Hardware Norman P. Jouppi, Chun-Fa Chang
1998	—	`conf`	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. 25 Years ISCA: Retrospectives and Reprints Norman P. Jouppi
1998	—	`conf`	Neon: A Single-Chip 3D Workstation Graphics Accelerator. Workshop on Graphics Hardware Joel McCormack, Bob McNamara, Chris Gianos, Larry Seiler, Norman P. Jouppi, Kenneth W. Correll
1998	—	`conf`	Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. 25 Years ISCA: Retrospectives and Reprints Norman P. Jouppi
1997	A*	`conf`	Complexity-Effective Superscalar Processors. ISCA Subbarao Palacharla, Norman P. Jouppi, James E. Smith
1997	A*	`conf`	Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1997	A*	`conf`	The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
1996	J	`jnl`	A speed, power, and supply noise evaluation of ECL driver circuits. IEEE J. Solid State Circuits Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon
1996	J	`jnl`	CACTI: an enhanced cache access and cycle time model. IEEE J. Solid State Circuits Steven J. E. Wilton, Norman P. Jouppi
1996	A*	`conf`	Register File Design Considerations in Dynamically Scheduled Processors. HPCA Keith I. Farkas, Norman P. Jouppi, Paul Chow
1995	A*	`conf`	How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA Keith I. Farkas, Norman P. Jouppi, Paul Chow
1994	A*	`conf`	Complexity/Performance Tradeoffs with Non-Blocking Loads. ISCA Keith I. Farkas, Norman P. Jouppi
1994	J	`jnl`	Designing, packaging, and testing a 300-MHz, 115 W ECL microprocessor. IEEE Micro Norman P. Jouppi, Patrick D. Boyle, John S. Fitch
1994	A*	`conf`	Tradeoffs in Two-Level On-Chip Caching. ISCA Norman P. Jouppi, Steven J. E. Wilton
1993	J	`jnl`	A 300-MHz 115-W 32-b bipolar ECL microprocessor. IEEE J. Solid State Circuits Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey W. Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, J. Leon Yang, William R. Hamburgen, John S. Fitch, Russell Kao
1993	A*	`conf`	Cache Write Policies and Performance. ISCA Norman P. Jouppi
1992	A*	`conf`	A Simulation Based Study of TLB Performance. ISCA J. Bradley Chen, Anita Borg, Norman P. Jouppi
1991	J	`jnl`	Computer Technology and Architecture: An Evolving Interaction. Computer John L. Hennessy, Norman P. Jouppi
1990	A*	`conf`	Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. ISCA Norman P. Jouppi
1989	J	`jnl`	A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance. IEEE J. Solid State Circuits Norman P. Jouppi, Jeffrey Y.-F. Tang
1989	A*	`conf`	A Unified Vector/Scalar Floating-Point Architecture. ASPLOS Norman P. Jouppi, Jonathan Bertoni, David W. Wall
1989	A*	`conf`	Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. ISCA Norman P. Jouppi
1989	A*	`conf`	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines. ASPLOS Norman P. Jouppi, David W. Wall
1989	C	`conf`	Integration and packaging plateaus of processor performance. ICCD Norman P. Jouppi
1989	J	`jnl`	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance. IEEE Trans. Computers Norman P. Jouppi
1988	J	`jnl`	Superscalar vs. superpipelined machines. SIGARCH Comput. Archit. News Norman P. Jouppi
1987	J	`jnl`	Derivation of Signal Flow Direction in MOS VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Norman P. Jouppi
1987	J	`jnl`	Timing Analysis and Performance Improvement of MOS VLSI Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Norman P. Jouppi
1983	A*	`conf`	Timing analysis for nMOS VLSI. DAC Norman P. Jouppi
1982	A*	`conf`	Hardware/Software Tradeoffs for Increased Performance. ASPLOS John L. Hennessy, Norman P. Jouppi, Forest Baskett, Thomas R. Gross, John Gill
1982	A*	`conf`	MIPS: A microprocessor architecture. MICRO John L. Hennessy, Norman P. Jouppi, Steven A. Przybylski, Christopher Rowen, Thomas R. Gross, Forest Baskett, John Gill
1982	—	`conf`	The MIPS Machine. COMPCON John L. Hennessy, Norman P. Jouppi, John Gill, Forest Baskett, Alex Strong, Thomas R. Gross, Christopher Rowen, Judson S. Leonard