Noriyuki Miura

122 papers A* 2A 1B 3C 6Misc 3Journal 50Unranked 57

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	29.5 A Sub-Gram Individual Plant Stress Sensor Tag for Smart Farming. ISSCC Daiki Nitto, Keishi Yanase, Yui Fujisawa, Jun Shiomi, Yoshihiro Midoh, Takuya Wadatsumi, Makoto Nagata, Ahmet Öncü, Constantine Sideris, Chetphilin Suriyasak, Yushi Ishibashi, Noriyuki Miura
2026	—	`conf`	PrometheusFree: Concurrent Detection of Laser Fault Injection Attacks in Optical Neural Networks. ASP-DAC Kota Nishida, Yoshihiro Midoh, Noriyuki Miura, Satoshi Kawakami, Alex Orailoglu, Jun Shiomi
2025	—	`conf`	20.1 A 3.5×3.5mm ISSCC Kotaro Naruse, Naru Kato, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Gaku Imamura, Genki Yoshikawa, Constantine Sideris, Noriyuki Miura
2025	—	`conf`	Hardware Trojan Detection by Fine-grained Power Domain Partitioning. ASP-DAC Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi
2025	—	`conf`	Physical/Machine-Learning Attacks Resilient Multi-Factor Authentication Employing Handwritten Challenge into Touch-Sensor PUF. WIFS Ruochen Wang, Kosuke Kawamura, Jun Shiomi, Yoshihiro Midoh, Yuichi Tanaka, Minoru Kuribayashi, Noriyuki Miura
2024	J	`jnl`	A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. ACM Trans. Embed. Comput. Syst. Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
2024	J	`jnl`	All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Trans. Cryptogr. Hardw. Embed. Syst. Haruka Hirata, Daiki Miyahara, Victor Arribas, Yang Li, Noriyuki Miura, Svetla Nikova, Kazuo Sakiyama
2024	—	`conf`	Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma
2024	B	`conf`	Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi
2024	J	`jnl`	SecONN: An Optical Neural Network Framework with Concurrent Detection of Thermal Fault Injection Attacks. CoRR Kota Nishida, Yoshihiro Midoh, Noriyuki Miura, Satoshi Kawakami, Jun Shiomi
2024	J	`jnl`	StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
2023	—	`conf`	A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura
2023	—	`conf`	A Triturated Sensing System. ISSCC Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	J	`jnl`	All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M. IACR Cryptol. ePrint Arch. Haruka Hirata, Daiki Miyahara, Victor Arribas, Yang Li, Noriyuki Miura, Svetla Nikova, Kazuo Sakiyama
2023	—	`conf`	DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
2022	J	`jnl`	A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
2022	—	`conf`	Accurate measurement of charge density in nanoscale particles using an aperture optimization of Fourier based phase reconstruction. Computational Imaging Takuma Okada, Yoshihiro Midoh, Koji Nakamae, Noriyuki Miura
2022	—	`conf`	DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
2022	J	`jnl`	Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. Makoto Nagata, Takuji Miki, Noriyuki Miura
2021	J	`jnl`	Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
2021	J	`jnl`	Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata
2021	C	`conf`	More Accurate and Robust PRNU-Based Source Camera Identification with 3-Step 3-Class Approach. IWDW Annjhih Hsiao, Takao Takenouchi, Hiroaki Kikuchi, Kazuo Sakiyama, Noriyuki Miura
2020	J	`jnl`	A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
2020	C	`conf`	A Key Recovery Algorithm Using Random Key Leakage from AES Key Schedule. ISITA Tomoki Uemura, Yohei Watanabe, Yang Li, Noriyuki Miura, Mitsugu Iwamoto, Kazuo Sakiyama, Kazuo Ohta
2020	J	`jnl`	A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	C	`conf`	A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	J	`jnl`	Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data. IEEE Embed. Syst. Lett. Kazuo Sakiyama, Tatsuya Fujii, Kohei Matsuda, Noriyuki Miura
2020	J	`jnl`	High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
2020	J	`jnl`	Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	J	`jnl`	A 0.72pJ/bit 400μm IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Makoto Nagata
2019	—	`conf`	A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki
2019	—	`conf`	A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC Makoto Nagata, Takuji Miki, Noriyuki Miura
2019	—	`conf`	Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	Misc	`conf`	Side-Channel Leakage of Alarm Signal for a Bulk-Current-Based Laser Sensor. Inscrypt Yang Li, Ryota Hatano, Sho Tada, Kohei Matsuda, Noriyuki Miura, Takeshi Sugawara, Kazuo Sakiyama
2019	J	`jnl`	Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
2018	J	`jnl`	A 286 F IEEE J. Solid State Circuits Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
2018	—	`conf`	A 286F ISSCC Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
2018	J	`jnl`	A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
2018	C	`conf`	Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
2018	J	`jnl`	Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
2017	—	`conf`	15.8 A permanent digital archive system based on 4F ISSCC Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
2017	J	`jnl`	A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2017	—	`conf`	An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2017	—	`conf`	Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
2017	J	`jnl`	Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
2017	C	`conf`	Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
2017	J	`jnl`	Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
2016	—	`conf`	A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2016	—	`conf`	Attack sensing against EM leakage and injection. ISOCC Noriyuki Miura, Shivam Bhasin
2016	J	`jnl`	Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Makoto Ikeda, Noriyuki Miura
2016	—	`conf`	On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST Kohei Matsuda, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Tatsuya Fujii, Kazuo Sakiyama
2016	A*	`conf`	PLL to the rescue: a novel EM fault countermeasure. DAC Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
2016	C	`conf`	Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2015	J	`jnl`	A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
2015	—	`conf`	A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2015	Misc	`conf`	At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
2015	A*	`conf`	EM attack sensor: concept, circuit, and design-automation methodology. DAC Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
2014	—	`conf`	12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2014	J	`jnl`	A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. IEEE J. Solid State Circuits Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2014	—	`conf`	A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2014	—	`conf`	A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata
2014	—	`conf`	An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
2014	J	`jnl`	Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
2014	J	`jnl`	EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014	A	`conf`	EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014	—	`conf`	On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
2014	J	`jnl`	Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
2014	—	`conf`	Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
2013	—	`conf`	3D clock distribution using vertically/horizontally-coupled resonators. ISSCC Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. ISSCC Wataru Mizuhara, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	J	`jnl`	A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines. IEEE J. Solid State Circuits Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers. ASP-DAC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2013	—	`conf`	A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×. ISSCC Noriyuki Miura, Mitsuko Saito, Masao Taguchi, Tadahiro Kuroda
2013	J	`jnl`	A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	B	`conf`	Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2013	—	`conf`	Immunity evaluation of inverter chains against RF power on power delivery network. EMC Compo Kumpei Yoshikawa, Yuji Harada, Noriyuki Miura, Noriaki Takeda, Yoshiyuki Saito, Makoto Nagata
2013	—	`conf`	Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
2012	J	`jnl`	6 W/25 mm IEICE Trans. Electron. Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards. IEEE J. Solid State Circuits Hayun Chung, Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	A 1 TB/s 1 pJ/b 6.4 mm IEEE J. Emerg. Sel. Topics Circuits Syst. Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda
2012	—	`conf`	A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. CICC Atsutake Kosuge, Wataru Mizuhara, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors. COOL Chips Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda
2012	J	`jnl`	A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. Kiichi Niitsu, Shusuke Kawai, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. ISSCC Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
2012	J	`jnl`	Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication. IEEE J. Solid State Circuits Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2012	J	`jnl`	Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card. IEEE J. Solid State Circuits Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda
2012	—	`conf`	Simultaneous data and power transmission using nested clover coils. ASP-DAC Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda
2011	—	`conf`	6W/25mm ISSCC Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda
2011	J	`jnl`	A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme. IEEE J. Solid State Circuits Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda
2011	—	`conf`	A 12Gb/s non-contact interface with coupled transmission lines. ISSCC Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2011	—	`conf`	A 2.7Gb/s/mm ISSCC Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda
2011	J	`jnl`	A 30 Gb/s/Link 2.2 Tb/s/mm IEEE J. Solid State Circuits Yasuhiro Take, Noriyuki Miura, Tadahiro Kuroda
2011	—	`conf`	Rotary coding for power reduction and S/N improvement in inductive-coupling data communication. A-SSCC Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2010	J	`jnl`	2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE J. Solid State Circuits Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2010	J	`jnl`	47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. IEEE Trans. Circuits Syst. I Regul. Pap. Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2010	—	`conf`	A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. ISSCC Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda
2010	—	`conf`	An 8Tb/s 1pJ/b 0.8mm ISSCC Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda
2009	—	`conf`	47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking. CICC Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2009	—	`conf`	A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	J	`jnl`	A High-Speed Inductive-Coupling Link With Burst Transmission. IEEE J. Solid State Circuits Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2009	B	`conf`	MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2008	J	`jnl`	A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. IEEE J. Solid State Circuits Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda
2008	J	`jnl`	A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array. IEEE J. Solid State Circuits Yoichi Yoshida, Noriyuki Miura, Tadahiro Kuroda
2008	—	`conf`	An 11Gb/s Inductive-Coupling Link with Burst Transmission. ISSCC Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2008	J	`jnl`	Constant Magnetic Field Scaling in Inductive-Coupling Data Link. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda
2007	—	`conf`	A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. ISSCC Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	A 1Tb/s 3W Inductive-Coupling Transceiver Chip. ASP-DAC Noriyuki Miura, Tadahiro Kuroda
2007	J	`jnl`	Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. IEEE J. Solid State Circuits Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2007	J	`jnl`	Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda
2007	—	`conf`	Wideband Inductive-coupling Interface for High-performance Portable System. CICC Hiroki Ishikuro, Noriyuki Miura, Tadahiro Kuroda
2006	J	`jnl`	A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Trans. Electron. Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
2006	J	`jnl`	A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Takayasu Sakurai, Tadahiro Kuroda
2006	—	`conf`	A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
2006	Misc	`conf`	Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication. VLSI Design Amit Kumar, Noriyuki Miura, Muhammad Muqsith, Tadahiro Kuroda
2005	J	`jnl`	Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. IEEE J. Solid State Circuits Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2004	—	`conf`	Cross talk countermeasures in inductive inter-chip wireless superconnect. CICC Noriyuki Miura, Daisuke Mizoguchi, Takayasu Sakurai, Tadahiro Kuroda
2004	—	`conf`	Practical methodology of post-layout gate sizing for 15% more power saving. ASP-DAC Noriyuki Miura, Naoki Kato, Tadahiro Kuroda