Nobutaro Shibata

16 papers A 1Journal 15

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Nobutaro Shibata, Mitsuo Nakamura
2017	J	`jnl`	A SOI Multi- IEICE Trans. Electron. Nobutaro Shibata, Mayumi Watanabe, Takako Ishihara
2016	J	`jnl`	A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications. IEICE Trans. Electron. Nobutaro Shibata, Yoshinori Gotoh, Takako Ishihara
2016	J	`jnl`	A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme. IEICE Trans. Electron. Nobutaro Shibata, Takako Ishihara
2015	J	`jnl`	An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍 IEEE Trans. Very Large Scale Integr. Syst. Nobutaro Shibata, Yusuke Ohtomo, Mika Nishisaka, Yasuhiro Sato
2015	J	`jnl`	High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. IEEE Trans. Very Large Scale Integr. Syst. Nobutaro Shibata, Yoshinori Gotoh
2010	J	`jnl`	A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells. IEEE J. Solid State Circuits Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama
2006	J	`jnl`	A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme. IEEE J. Solid State Circuits Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki
2005	J	`jnl`	A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation. IEICE Trans. Electron. Takakuni Douseki, Toshishige Shimamura, Nobutaro Shibata
2002	J	`jnl`	A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell. IEEE J. Solid State Circuits Nobutaro Shibata, Mayumi Watanabe, Yasuyuki Tanabe
2001	J	`jnl`	A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. IEEE J. Solid State Circuits Nobutaro Shibata, Mayumi Watanabe, Yasuhiro Sato, Takako Ishihara, Yukio Komine
2000	J	`jnl`	1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs. IEEE J. Solid State Circuits Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada
1999	J	`jnl`	A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers. IEEE J. Solid State Circuits Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe
1998	J	`jnl`	A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's. IEEE J. Solid State Circuits Hiroki Morimura, Nobutaro Shibata
1996	A	`conf`	A 1-V 1-Mb SRAM for portable equipment. ISLPED Hiroki Morimura, Nobutaro Shibata
1996	J	`jnl`	Two-chip MPEG-2 video encoder. IEEE Micro Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato