Nobuki Kajihara

15 papers B 1C 1Misc 2Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2024 C conf
FPGA Implementation for Large Scale Reservoir Computing based on Chaotic Boltzmann Machine.
ISCAS
Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara, Hakaru Tamukoh
2001 B conf
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
FPL
Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
2001 — conf
Implementation of a Gate-Level Evolvable Hardware Chip.
ICES
Masaya Iwata, Isamu Kajitani, Yong Liu, Nobuki Kajihara, Tetsuya Higuchi
2000 Misc conf
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
FCCM
Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara
1999 — conf
An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller.
AAAI/IAAI
Isamu Kajitani, Tsutomu Hoshino, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
1999 J jnl
Evolvable Hardware Chips for Industrial Applications.
Commun. ACM
Tetsuya Higuchi, Nobuki Kajihara
1999 — conf
Evolvable Hardware Chips for Neural Network Applications.
ICANNGA
Isamu Kajitani, Masahiro Murakawa, Nobuki Kajihara, Masaya Iwata, Hidenori Sakanashi, Tetsuya Higuchi
1999 J jnl
Real-world applications of analog and digital evolvable hardware .
IEEE Trans. Evol. Comput.
Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
1999 J jnl
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing.
IEEE Trans. Computers
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi
1998 — conf
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
ICES
Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi
1998 — conf
Evolvable Hardware Chip for High Precision Printer Image Compression.
AAAI/IAAI
Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi
1996 — conf
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method.
Parcella
Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara
1996 Misc conf
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method.
FCCM
Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara
1989 J jnl
MAN-YO: Mixed level parallel logic simulation engine.
Syst. Comput. Jpn.
Nobuhiko Koike, Toshiyuki Nakata, Nobuki Kajihara
1988 J jnl
Parallel neural network simulation machine: Neuman.
Neural Networks
Nobuki Kajihara, Satoshi Matsushita, Toshiyuki Nakata, Nobuhiko Koike