Nobuhiro Tomabechi

16 papers C 2Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2009 — conf
Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm.
ICE-GIC
Nobuhiro Tomabechi, Yoshichika Fujioka
2005 — conf
VLSI architecture based on packet data transfer scheme and its application.
ISCAS (2)
Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
2002 J jnl
Design of a high-speed RSA encryption processor based on the residue table for redundant binary numbers.
Syst. Comput. Jpn.
Nobuhiro Tomabechi, Teruki Ito
2001 — conf
Defect-tolerance design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.
ICECS
Nobuhiro Tomabechi, Teruki Ito
2000 J jnl
Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units.
Syst. Comput. Jpn.
Yoshichika Fujioka, Nobuhiro Tomabechi
2000 C conf
Design of a high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers.
ISCAS
Nobuhiro Tomabechi, Teruki Ito
1999 — conf
Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems.
DFT
Nobuhiro Tomabechi
1998 J jnl
Redundancy design of a wafer scale two-dimensional FFT processor.
Syst. Comput. Jpn.
Shyouji Kanazawa, Nobuhiro Tomabechi
1997 J jnl
CAI oriented algorithm for Boolean-function minimization based on the ternaryKarnaugh map.
Syst. Comput. Jpn.
Nobuhiro Tomabechi
1997 J jnl
Redundancy design of a wafer scale and high-speed FFT processor.
Syst. Comput. Jpn.
Nobuhiro Tomabechi, Shyouji Kanazawa
1997 J jnl
The effect of hardware needed for redundant interconnection lines and exchangingswitches on the yield of VLSI chips with redundan.
Syst. Comput. Jpn.
Nobuhiro Tomabechi
1996 J jnl
Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length.
J. Robotics Mechatronics
Yoshichika Fujioka, Nobuhiro Tomabechi
1996 J jnl
WSI oriented design for highly reliable systems based on the residue number system.
Syst. Comput. Jpn.
Nobuhiro Tomabechi
1991 J jnl
A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems.
Syst. Comput. Jpn.
Nobuhiro Tomabechi
1989 C conf
Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems.
ICCD
Nobuhiro Tomabechi
1986 J jnl
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.
Syst. Comput. Jpn.
Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi