Nobu Matsumoto

19 papers A* 3A 2C 1Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2020 — conf
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm
ISSCC
Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto
2020 — conf
A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR.
VLSI Circuits
Tuan Thanh Ta, Hiroshi Kubota, Koichi Kokubun, Toshiki Sugimoto, Masatoshi Hirono, Mitsuhiro Sengoku, Hisaaki Katagiri, Hidenori Okuni, Satoshi Kondo, Shinichi Ohtsuka, Honam Kwon, Keita Sasaki, Yutaka Ota, Kazuhiro Suzuki, Katsuyuki Kimura, Kentaro Yoshioka, Akihide Sai, Nobu Matsumoto
2020 J jnl
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm
IEEE J. Solid State Circuits
Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto
2019 — conf
Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR.
COOL CHIPS
Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto
2018 J jnl
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.
IEEE J. Solid State Circuits
Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
2018 — conf
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique.
ISSCC
Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
2018 — conf
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR.
COOL CHIPS
Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto
2013 A conf
A near-future prediction method for low power consumption on a many-core processor.
DATE
Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto
2010 — conf
A new compilation technique for SIMD code generation across basic block boundaries.
ASP-DAC
Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai
2009 A conf
Design and implementation of scalable, transparent threads for multi-core media processor.
DATE
Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyoshi, Ryuichiro Ohyama, Nobuhiro Nonogaki, Koji Kitayama, Tatsuya Mori, Yasuyuki Ueda, Hideho Arakida, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi, Nobu Matsumoto
2007 J jnl
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto
2006 Misc conf
Pack instruction generation for media pUsing multi-valued decision diagram.
CODES+ISSS
Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa
2003 J jnl
A single-chip MPEG-2 codec based on customizable media embedded processor.
IEEE J. Solid State Circuits
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Mitsuo Saito, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
2002 — conf
A single-chip MPEG-2 codec based on customizable media microprocessor.
CICC
Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Shuji Michinaka, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui
2002 C conf
Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture.
ICCD
Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui
2001 A* conf
A New Verification Methodology for Complex Pipeline Behavior.
DAC
Kazuyoshi Kohno, Nobu Matsumoto
1993 A* conf
A Compaction Method for Full Chip VLSI Layouts.
DAC
Joseph Dao, Nobu Matsumoto, Tsuneo Hamai, Chusei Ogawa, Shojiro Mori
1991 J jnl
Hierarchical symbolic design methodology for large-scale data paths.
IEEE J. Solid State Circuits
Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori
1990 A* conf
Datapath Generator Based on Gate-Level Symbolic Layout.
DAC
Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori